Date: Tue, 03 Sep 2019 14:07:32 -0000 From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r346562 - stable/11/share/man/man7 Message-ID: <201904221526.x3MFQMfS074240@repo.freebsd.org>
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Author: ian Date: Mon Apr 22 15:26:21 2019 New Revision: 346562 URL: https://svnweb.freebsd.org/changeset/base/346562 Log: MFC r337364: Document 64-bit arm in terms of arch name (aarch64) not machine (arm64). Other architectures are documented in terms of the name that is displayed by 'uname -p', aka MACHINE_ARCH and TARGET_ARCH in the build system, now aarch64 matches the rest of them. PR: 220297 Modified: stable/11/share/man/man7/arch.7 Directory Properties: stable/11/ (props changed) Modified: stable/11/share/man/man7/arch.7 ============================================================================== --- stable/11/share/man/man7/arch.7 Mon Apr 22 15:23:06 2019 (r346561) +++ stable/11/share/man/man7/arch.7 Mon Apr 22 15:26:21 2019 (r346562) @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 16, 2017 +.Dd August 5, 2018 .Dt ARCH 7 .Os .Sh NAME @@ -90,12 +90,12 @@ architectures, the final release. .Pp .Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release" .It Sy Architecture Ta Sy Initial Release Ta Sy Final Release +.It aarch64 Ta 11.0 .It alpha Ta 3.2 Ta 6.4 .It amd64 Ta 5.1 .It arm Ta 6.0 .It armeb Ta 8.0 .It armv6 Ta 10.0 -.It arm64 Ta 11.0 .It ia64 Ta 5.0 Ta 10.x .It i386 Ta 1.0 .It mips Ta 8.0 @@ -161,7 +161,7 @@ Examples are: .It Dv powerpc64 Ta Dv powerpc .It Dv mips64* Ta Dv mips* .El -.Dv arm64 +.Dv aarch64 currently does not support execution of .Dv armv6 binaries, even if the CPU implements @@ -188,11 +188,11 @@ require only 4-byte alignment for 64-bit integers. Machine-dependent type sizes: .Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t" .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t +.It aarch64 Ta 8 Ta 16 Ta 8 .It amd64 Ta 8 Ta 16 Ta 8 .It arm Ta 4 Ta 8 Ta 8 .It armeb Ta 4 Ta 8 Ta 8 .It armv6 Ta 4 Ta 8 Ta 8 -.It arm64 Ta 8 Ta 16 Ta 8 .It i386 Ta 4 Ta 12 Ta 4 .It mips Ta 4 Ta 8 Ta 8 .It mipsel Ta 4 Ta 8 Ta 8 @@ -217,11 +217,11 @@ variants of powerpc. .Ss Endianness and Char Signedness .Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness" .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness +.It aarch64 Ta little Ta unsigned .It amd64 Ta little Ta signed .It arm Ta little Ta unsigned .It armeb Ta big Ta unsigned .It armv6 Ta little Ta unsigned -.It arm64 Ta little Ta unsigned .It i386 Ta little Ta signed .It mips Ta big Ta signed .It mipsel Ta little Ta signed @@ -242,11 +242,11 @@ variants of powerpc. .Ss Page Size .Bl -column -offset indent "Sy Architecture" "Sy Page Sizes" .It Sy Architecture Ta Sy Page Sizes +.It aarch64 Ta 4K, 2M, 1G .It amd64 Ta 4K, 2M, 1G .It arm Ta 4K .It armeb Ta 4K .It armv6 Ta 4K, 1M -.It arm64 Ta 4K, 2M, 1G .It i386 Ta 4K, 2M (PAE), 4M .It mips Ta 4K .It mipsel Ta 4K @@ -267,11 +267,11 @@ variants of powerpc. .Ss Floating Point .Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double" .It Sy Architecture Ta Sy float, double Ta Sy long double +.It aarch64 Ta hard Ta soft, quad precision .It amd64 Ta hard Ta hard, 80 bit .It arm Ta soft Ta soft, double precision .It armeb Ta soft Ta soft, double precision .It armv6 Ta hard(1) Ta hard, double precision -.It arm64 Ta hard Ta soft, quad precision .It i386 Ta hard Ta hard, 80 bit .It mips Ta soft Ta identical to double .It mipsel Ta soft Ta identical to double @@ -319,11 +319,11 @@ is not used on Architecture-specific macros: .Bl -column -offset indent "Sy Architecture" "Sy Predefined macros" .It Sy Architecture Ta Sy Predefined macros +.It aarch64 Ta Dv __aarch64__ .It amd64 Ta Dv __amd64__, Dv __x86_64__ .It arm Ta Dv __arm__ .It armeb Ta Dv __arm__ .It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6 -.It arm64 Ta Dv __aarch64__ .It i386 Ta Dv __i386__ .It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32 .It mipsel Ta Dv __mips__, Dv __mips_o32
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