From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 22:34:42 2010 Return-Path: Delivered-To: mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 29F0F1065677 for ; Sat, 17 Jul 2010 22:34:42 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id DFE808FC14 for ; Sat, 17 Jul 2010 22:34:41 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6HMTcxT015499; Sat, 17 Jul 2010 16:29:38 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 17 Jul 2010 16:30:02 -0600 (MDT) Message-Id: <20100717.163002.13040899182090510.imp@bsdimp.com> To: c.jayachandran@gmail.com From: "M. Warner Losh" In-Reply-To: References: <20100715.161926.175946041864758761.imp@bsdimp.com> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Cc: mips@FreeBSD.org Subject: Re: Review X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 22:34:42 -0000 In message: "Jayachandran C." writes: : On Fri, Jul 16, 2010 at 3:49 AM, M. Warner Losh wrot= e: : > OK. =A0Please find enclosed a minor cleanup diff for assembler file= s. : > It moves ITLBNOPFIX and HAZARD_DELAY into a common header, as well = as : > replacing MIPS_CPU_NOP_DELAY with HAZARD_DELAY. : > : > The only real change is increasing the number of nops in a few plac= es : > from 4 to 5. : > : > This is in preparation for making these (a) much shorter and (b) : > optimizing for specific CPUs... =A0mips32/mips64 define ssnop to de= al : > with the super-scaler effects (so ITLBNOPFIX can be shorter), and : > mips32r2 and mips64r2 have eh, which can help with HAZARD_DELAY. : > : > The latter will need some careful study of the docs to make sure th= at : > the proper number of instructions are executed (which is why I'm no= t : > doing it yet :). =A0The former is just shuffling deck chairs, so sh= ould be : > invisible to people. : > : > Comments? : = : There is a mips_barrier() in cpufunc.h too which does similar things = - : and is confusingly named - we can to get rid of that too in a similar= : way. Yea, there's similar things in that file to the other stuff... : Another cleanup I wanted to do for sometime is to get the status : register settings into a header files and avoid the ifdef everywhere.= I've wanted that too.... : Maybe cpuregs.h (or cpufunc.h) can add cpu_xlr.h/cpu_octeon.h etc : which will have hazard/status/extra registers for the specific cpu. Yea, that's a good idea, I think... There's also lots of places we disable interrupts by writing to STATUS, but that could be dealt with EI or DI... Warner : Thanks, : JC. : = : =