From owner-p4-projects@FreeBSD.ORG Mon Apr 13 08:06:35 2009 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id ABEEC1065676; Mon, 13 Apr 2009 08:06:34 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 4E74F106566C for ; Mon, 13 Apr 2009 08:06:34 +0000 (UTC) (envelope-from andrew@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 22CE98FC0A for ; Mon, 13 Apr 2009 08:06:34 +0000 (UTC) (envelope-from andrew@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n3D86YFw019059 for ; Mon, 13 Apr 2009 08:06:34 GMT (envelope-from andrew@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n3D86YIt019057 for perforce@freebsd.org; Mon, 13 Apr 2009 08:06:34 GMT (envelope-from andrew@freebsd.org) Date: Mon, 13 Apr 2009 08:06:34 GMT Message-Id: <200904130806.n3D86YIt019057@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to andrew@freebsd.org using -f From: Andrew Turner To: Perforce Change Reviews Cc: Subject: PERFORCE change 160554 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Apr 2009 08:06:36 -0000 http://perforce.freebsd.org/chv.cgi?CH=160554 Change 160554 by andrew@andrew_bender on 2009/04/13 08:06:17 Rename the NAND flash registers to be device specific Add a subset of the S3C2440 registers Affected files ... .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#8 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2440reg.h#2 edit Differences ... ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#8 (text+ko) ==== @@ -62,17 +62,17 @@ /* NAND Flash controller */ #define S3C2410_NANDFC_SIZE 0x18 /* NANDFC_NFCONF */ -#define NFCONF_ENABLE (1<<15) /* NAND controller enabled */ -#define NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */ -#define NFCONF_FCE (1<<11) /* Flash chip enabled */ -#define NFCONF_TACLS (7<<8) /* CLE and ALE duration */ -#define NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */ -#define NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */ -#define NANDFC_NFCMD 0x04 /* command */ -#define NANDFC_NFADDR 0x08 /* address */ -#define NANDFC_NFDATA 0x0c /* data */ -#define NANDFC_NFSTAT 0x10 /* operation status */ -#define NANDFC_NFECC 0x14 /* ecc */ +#define S3C2410_NFCONF_ENABLE (1<<15) /* NAND controller enabled */ +#define S3C2410_NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */ +#define S3C2410_NFCONF_FCE (1<<11) /* Flash chip enabled */ +#define S3C2410_NFCONF_TACLS (7<<8) /* CLE and ALE duration */ +#define S3C2410_NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */ +#define S3C2410_NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */ +#define S3C2410_NANDFC_NFCMD 0x04 /* command */ +#define S3C2410_NANDFC_NFADDR 0x08 /* address */ +#define S3C2410_NANDFC_NFDATA 0x0c /* data */ +#define S3C2410_NANDFC_NFSTAT 0x10 /* operation status */ +#define S3C2410_NANDFC_NFECC 0x14 /* ecc */ /* GPIO */ #define S3C2410_GPIO_SIZE 0xb4 ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2440reg.h#2 (text+ko) ==== @@ -57,6 +57,25 @@ #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) +/* NAND Flash controller */ +#define S3C2440_NANDFC_SIZE 0x40 + +#define S3C2440_NANDFC_NFCONT 0x04 +#define S3C2440_NFCONT_LOCK_TIGHT (1<<13) /* Lock part of the NAND */ +#define S3C2440_NFCONT_SOFT_LOCK (1<<12) /* Soft lock part of the NAND */ +#define S3C2440_NFCONT_ILLEGAL_ACC_INT (1<<10) /* Illegal access interrupt */ +#define S3C2440_NFCONT_RNB_INT (1<<9) /* RnB transition interrupt */ +#define S3C2440_NFCONT_RNB_TRANS_MODE (1<<8) /* RnB transition mode */ +#define S3C2440_NFCONT_SPARE_ECC_LOCK (1<<6) /* Lock spare ECC generation */ +#define S3C2440_NFCONT_MAIN_ECC_LOCK (1<<5) /* Lock main ECC generation */ +#define S3C2440_NFCONT_INIT_ECC (1<<4) /* Init ECC encoder/decoder */ +#define S3C2440_NFCONT_NCE (1<<1) /* NAND Chip select */ +#define S3C2440_NFCONT_ENABLE (1<<0) /* Enable the controller */ +#define S3C2440_NANDFC_NFCMMD 0x08 +#define S3C2440_NANDFC_NFADDR 0x0c +#define S3C2440_NANDFC_NFDATA 0x10 +#define S3C2440_NANDFC_NFSTAT 0x20 + /* GPIO */ #define S3C2440_GPIO_SIZE 0xd0