Date: Wed, 17 Feb 1999 14:44:15 -0800 (PST) From: Matthew Dillon <dillon@apollo.backplane.com> To: "John S. Dyson" <dyson@iquest.net> Cc: dyson@iquest.net, tlambert@primenet.com, toasty@home.dragondata.com, mike@smith.net.au, hackers@FreeBSD.ORG Subject: Re: vm_page_zero_fill Message-ID: <199902172244.OAA11578@apollo.backplane.com> References: <199902172139.QAA70278@y.dyson.net>
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:>
:> This is robbing Peter to pay Paul; in a way. The base assumption
:> that you are hiding is that you aren't constrained by memory
:> bandwidth. This isn't true if you are nearly saturating a PCI
:> bus with 4 BT848's (to pick the highest memory bandwidth application
:> I know about).
:>
:I just realized something:
:
: Memory bandwidth is >> PCI bandwidth on good designs. I believe
:that the PCI and memory busses are decoupled on at least some X86 machines.
:
:--
:John | Never try to teach a pig to sing,
:dyson@iquest.net | it makes one look stupid
:jdyson@nc.com | and it irritates the pig.
Main memory and the PCI bus are decoupled and buffered with FIFOs on all
designs that I know of. That's what all those burst and write posting
options are in the chipset BIOS. This is why you want to use DMA... it
won't (much) stall main memory or the cpu while transfering data to or
from the PCI bus.
-Matt
Matthew Dillon
<dillon@backplane.com>
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