From owner-freebsd-hackers Sun Mar 24 10:42:05 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id KAA17138 for hackers-outgoing; Sun, 24 Mar 1996 10:42:05 -0800 (PST) Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id KAA17132 for ; Sun, 24 Mar 1996 10:42:04 -0800 (PST) Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id LAA09968; Sun, 24 Mar 1996 11:35:08 -0700 From: Terry Lambert Message-Id: <199603241835.LAA09968@phaeton.artisoft.com> Subject: Re: FreeBSD and MMX To: uhclem@nemesis.lonestar.org (Frank Durda IV) Date: Sun, 24 Mar 1996 11:35:08 -0700 (MST) Cc: hackers@FreeBSD.ORG In-Reply-To: from "Frank Durda IV" at Mar 23, 96 10:30:00 pm X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-hackers@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk > The MMX processor adds several new 64-bit registers to the system > that are off in a corner, similar to the way the floating point > registers and opcodes are handled. There are new opcodes for gettings > things in and out of the new registers, plus new opcodes that perform > operations on the new registers. (Again, this is real similar to how > the floating point subsystem works.) According to Intels WWW FAQ, they > didn't have mess with the integer microcode much, thus lowering the risk > of a compatibility flaw of some sort. > > The new operations are all geared to things found in graphics, > compression, and other repetitive algorithms. For example, it > is possible to load eight 8-bit values into one of these new > registers and perform eight adds simultaneously, without having the Carry > bits roll over from one eight-bit value to the next. There are > also some codes to do max/min type functions to avoid signed rollover. One question: soes this handle cache line byte addressing? Specifically, is it possible to have a non-aligned src and destination address on a copy and have it fixed up by the processor setting its pointer into the cache line to save multiple fetch cycles per copy unit? Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.