From owner-freebsd-hackers@FreeBSD.ORG Sat Mar 28 11:20:44 2015 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C3E01148 for ; Sat, 28 Mar 2015 11:20:44 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 7F4C8600 for ; Sat, 28 Mar 2015 11:20:44 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.84 (FreeBSD)) (envelope-from ) id 1Ybon5-000GRO-I0 for freebsd-hackers@freebsd.org; Sat, 28 Mar 2015 14:20:35 +0300 Date: Sat, 28 Mar 2015 14:20:35 +0300 From: Slawa Olhovchenkov To: freebsd-hackers@freebsd.org Subject: irq cpu binding Message-ID: <20150328112035.GZ23643@zxy.spb.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Mar 2015 11:20:44 -0000 Can someone describe how on FreeBSD/amd64 do interrupt handling? Can be interrupt handler (hardware interrupt) direct dispatch to specific CPU core (and only to this core)? Can be all work be only on this core (ithread, device driver interrupt handler, finalise)?