Date: Thu, 28 Aug 97 10:00:39 -0700 From: "Mike Burgett" <mburgett@awen.com> To: "hardware@freebsd.org" <hardware@freebsd.org> Subject: Fwd: K6 Linux Re-Compile Issue Message-ID: <199708281700.KAA16401@dragon.awen.com>
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FWIW, I just got the following from AMD tech support, regarding the problems I
had reported with my initial K6 and running 'make world'
==================BEGIN FORWARDED MESSAGE==================
>Date: Thu, 28 Aug 1997 08:47:35 -0700
>From: AMD Tech Support <hwsupt1@brahms.amd.com>
>Organization: AMD Tech Hotline
>Subject: K6 Linux Re-Compile Issue
Hello,
AMD recently received reports from a limited number of users having
intermittent problems while running core re-compiles of the Linux
shareware operating system. Our systems engineering group has duplicated
the observation and determined that it is related to a previously know
erratum. Full technical details of this erratum are documented in
section 2.6.2 of the AMD-K6 MMX Enhanced Processor Revision Guide posted
on our website, www.amd.com. Users that feel they are being affected by
this problem, should contact AMD s support line at (408) 749-3060 and
ask for Dan Hingle or Glen Garcia.
Regards,
Technical Support
===================END FORWARDED MESSAGE===================
Here's the section of the errata that they apparently didn't feel like
appending:
2.6.2 Re-execution of Instructions Due to Self-Modifying Code
Products Affected. B stepping
Normal Specified Operation. If the processor detects a potential
self-modifying code condition, the processor performs specific
internal actions to ensure that instruction execution occurs in
the correct manner.
Non-conformance. If:
- The target of a transfer control instruction is fetched and
loaded into the processor s Branch Target Cache (BTC)
- This transfer control instruction is speculatively executed
and hits in the BTC
- An instruction (Instruction A ) is executed that causes the
processor to detect a potential self-modifying code condition
relative to the transfer control target that resides in the BTC
- Instruction A is followed by a register-modifying
instruction(s) in the form of:
A long-decoded instruction, or;
One or two short-decoded instructions
- The transfer control instruction that was speculatively
executed follows the register-modifying instruction(s)
within approximately 1-9 instructions
- Certain other relative internal pipeline timing conditions
must occur
then: the long-decoded instruction, or the short-decoded
instruction(s), is executed twice.
Potential Effect on System. If software is not affected by the
re-execution of the register-modifying instruction(s) for
instance, loading immediate data into a general purpose register
then this erratum has no effect on the system. However, if any
of the instructions that are re-executed change the state of the
system from the state that would be achieved by the normal
specified operation for instance, incrementing a register by one
then this erratum can lead to unpredictable system behavior.
Suggested Workaround. None.
Resolution Status. This erratum will be corrected in a future
stepping of the AMD-K6 processor.
--Mike
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