From owner-cvs-src Tue Mar 4 13: 9:10 2003 Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 85E3637B405 for ; Tue, 4 Mar 2003 13:09:06 -0800 (PST) Received: from mail.speakeasy.net (mail13.speakeasy.net [216.254.0.213]) by mx1.FreeBSD.org (Postfix) with ESMTP id CC6E643F93 for ; Tue, 4 Mar 2003 13:09:04 -0800 (PST) (envelope-from jhb@FreeBSD.org) Received: (qmail 15328 invoked from network); 4 Mar 2003 21:09:11 -0000 Received: from unknown (HELO server.baldwin.cx) ([216.27.160.63]) (envelope-sender ) by mail13.speakeasy.net (qmail-ldap-1.03) with DES-CBC3-SHA encrypted SMTP for ; 4 Mar 2003 21:09:11 -0000 Received: from laptop.baldwin.cx (gw1.twc.weather.com [216.133.140.1]) by server.baldwin.cx (8.12.6/8.12.6) with ESMTP id h24L6WhT046082; Tue, 4 Mar 2003 16:06:32 -0500 (EST) (envelope-from jhb@FreeBSD.org) Message-ID: X-Mailer: XFMail 1.5.2 on FreeBSD X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit MIME-Version: 1.0 In-Reply-To: <3E650F02.AA2109F2@imimic.com> Date: Tue, 04 Mar 2003 16:09:17 -0500 (EST) From: John Baldwin To: "Alan L. Cox" Subject: Re: cvs commit: src/sys/conf options.i386 src/sys/i386/conf NOTE Cc: cvs-all@FreeBSD.org, cvs-src@FreeBSD.org, src-committers@FreeBSD.org Sender: owner-cvs-src@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On 04-Mar-2003 Alan L. Cox wrote: > John Baldwin wrote: >> >> jhb 2003/03/04 12:24:53 PST >> >> FreeBSD src repository >> >> Modified files: >> sys/conf options.i386 >> sys/i386/conf NOTES >> sys/i386/i386 mp_machdep.c >> Log: >> Wrap the hyperthreading support code with the HTT kernel option. >> Hyperthreading support is now off unless the HTT option is added. >> >> MFC-after: 3 days >> >> Revision Changes Path >> 1.185 +1 -0 src/sys/conf/options.i386 >> 1.1078 +1 -0 src/sys/i386/conf/NOTES >> 1.204 +21 -0 src/sys/i386/i386/mp_machdep.c > > How hard would it be to configure the system so that the 2nd logical CPU > on a chip did nothing but field interrupts? Given that interrupts are > going to pollute the cache and TLB anyway, two of the detrimental > effects of hyperthreading are already "bought and paid for". That would be a bit trickier and involve lots of changes to the I/O APIC stuff. The other possiblity is to dink with TPR, but there are some really bad failure modes with using TPR it seems on some boxes so I'd rather not do that. -- John Baldwin <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-src" in the body of the message