Date: Fri, 18 Jan 2002 22:50:23 -0500 (EST) From: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> To: mime@traveller.cz Cc: arch@FreeBSD.org Subject: Re: 64 bit counters again Message-ID: <200201190350.g0J3oNN08944@khavrinen.lcs.mit.edu> In-Reply-To: <mit.lcs.mail.freebsd-arch/Pine.BSF.4.41.0201190128440.5921-100000@prg.traveller.cz> References: <mit.lcs.mail.freebsd-arch/3C48A0E7.F97BC01@mindspring.com>
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In article <mit.lcs.mail.freebsd-arch/Pine.BSF.4.41.0201190128440.5921-100000@prg.traveller.cz> you write: >> Yes. IA64. SPARC 9b (SPARC64) and Alpha, which are 64 >> bits, require locks, since they don't have the ability to >> do an atomic "lock; cmpxchg8b". > >Can they do "lock; add const,(mem)" in 32 or 64 bit? Terry is talking out of his ear again. Alpha most definitely does have 64-bit load-linked/store-conditional, which is entirely equivalent to i386's 64-bit compare-exchange. (For some reason in the Alpha ARM it's called ``load locked'' instead.) If we cared about running on MIPS architectures, they have LL/SC as well. SPARC v9 has 64-bit compare-and-swap (although unlike in IA32 a memory barrier is also required); see the SPARC v9 Architecture Reference Manual. IA64 has 64-bit compare-exchange as well; see the Itanium Architecture Software Developer's Manual, volume 2 (Intel document number 245318-003), where there's a whole section on implementing synchronization primitives on IA84; it also has an atomic FETCHADD instruction which I didn't bother to look more closely at. -GAWollman -- Garrett A. Wollman | O Siem / We are all family / O Siem / We're all the same wollman@lcs.mit.edu | O Siem / The fires of freedom Opinions not those of| Dance in the burning flame MIT, LCS, CRS, or NSA| - Susan Aglukark and Chad Irschick To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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