Date: Tue, 12 Nov 2019 19:50:19 +1100 From: Peter Jeremy <peter@rulingia.com> To: mmel@FreeBSD.org Cc: freebsd-arm@freebsd.org Subject: Rock64 clock errors following r354558 Message-ID: <20191112085019.GC50716@server.rulingia.com>
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--i0/AhcQY5QxfSsSZ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Michal, Somewhere between r354439 and r354592, my Rock64 (RK3328) has started reporting errors setting the clocks on aclk_bus_pre and aclk_peri_pre. My best guess is that it's somewhere in r354554..r354558. I have had a quick look and noting jumps out at me so I'm wondering if you have any ideas. The relevant non-verbose messages are now: rk3328_cru0: <Rockchip RK3328 Clock and Reset Unit> mem 0xff440000-0xff440f= ff on ofwbus0 rk3328_cru0: cannot get parent at idx 6 Cannot set frequency for clk: aclk_bus_pre, error: 34 rk3328_cru0: Failed to set aclk_bus_pre to a frequency of 15000000 Cannot set frequency for clk: aclk_peri_pre, error: 34 rk3328_cru0: Failed to set aclk_peri_pre to a frequency of 15000000 The "cannot get parent" has been around for as long as I can tell but the "cannot set frequency" errors are both new. Looking back, my previous verbose boot was at r354239 and it shows: rk3328_cru0: cannot get assigned clock at idx 5 rk3328_cru0: cannot get parent at idx 6 rk3328_cru0: Set aclk_bus_pre to 15000000 rk3328_cru0: Set aclk_peri_pre to 15000000 rk3328_cru0: cannot get assigned clock at idx 8 With a verbose boot at r354607 (including some additional debug printf's), it now shows: rk3328_cru0: cannot get assigned clock at idx 5 rk3328_cru0: cannot get parent for aclk_bus_pre at idx 6 rk_clk_composite_set_freq:(aclk_bus_pre)Finding best parent/div for target = freq of 15000000 rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent cpll (0) at fre= q 594000000 rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent gpll (1) at fre= q 576000000 rk_clk_composite_set_freq:(aclk_bus_pre)Best divisor is 0 Cannot set frequency for clk: aclk_bus_pre, error: 34 rk_clk_composite_recalc:(aclk_bus_pre)Read: muxdiv_offset=3D100, val=3D2501 rk_clk_composite_recalc:(aclk_bus_pre)parent_freq=3D576000000, div=3D6 rk_clk_composite_recalc:(aclk_bus_pre)Final freq=3D96000000 rk_clk_composite_recalc:(hclk_bus_pre)Read: muxdiv_offset=3D104, val=3D1113 rk_clk_composite_recalc:(hclk_bus_pre)parent_freq=3D96000000, div=3D2 rk_clk_composite_recalc:(hclk_bus_pre)Final freq=3D48000000 rk_clk_composite_recalc:(pclk_bus_pre)Read: muxdiv_offset=3D104, val=3D1113 rk_clk_composite_recalc:(pclk_bus_pre)parent_freq=3D96000000, div=3D2 rk_clk_composite_recalc:(pclk_bus_pre)Final freq=3D48000000 rk3328_cru0: Failed to set aclk_bus_pre to a frequency of 15000000 rk_clk_composite_set_freq:(aclk_peri_pre)Finding best parent/div for target= freq of 15000000 rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent cpll (0) at fr= eq 594000000 rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent gpll (1) at fr= eq 576000000 rk_clk_composite_set_freq:(aclk_peri_pre)Best divisor is 0 Cannot set frequency for clk: aclk_peri_pre, error: 34 rk_clk_composite_recalc:(aclk_peri_pre)Read: muxdiv_offset=3D170, val=3D4143 rk_clk_composite_recalc:(aclk_peri_pre)parent_freq=3D576000000, div=3D4 rk_clk_composite_recalc:(aclk_peri_pre)Final freq=3D144000000 rk_clk_composite_recalc:(pclk_peri)Read: muxdiv_offset=3D0, val=3D40c8 rk_clk_composite_recalc:(pclk_peri)parent_freq=3D144000000, div=3D1 rk_clk_composite_recalc:(pclk_peri)Final freq=3D144000000 rk_clk_composite_recalc:(hclk_peri)Read: muxdiv_offset=3D0, val=3D40c8 rk_clk_composite_recalc:(hclk_peri)parent_freq=3D144000000, div=3D5 rk_clk_composite_recalc:(hclk_peri)Final freq=3D28800000 rk3328_cru0: Failed to set aclk_peri_pre to a frequency of 15000000 rk3328_cru0: cannot get assigned clock at idx 8 --=20 Peter Jeremy --i0/AhcQY5QxfSsSZ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQKTBAEBCgB9FiEE7rKYbDBnHnTmXCJ+FqWXoOSiCzQFAl3KckZfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEVF QjI5ODZDMzA2NzFFNzRFNjVDMjI3RTE2QTU5N0EwRTRBMjBCMzQACgkQFqWXoOSi CzRTUw/9HbBX9qJZPsRJR109fcPMY2VPsQXulRgWlqhJWqj9QIpxAoJZyaqyOYDk OJuK/d0Rz+y4fWm+ppTCjKoyyuFTrusGUnKnsILTyL7NPG3Si2fh1pvYss6YddC9 mRpCS3TB3neVhTO7Js6Y6WAKAugBZLKoD7a1eADzflCS304AD0pAS6XaoiW9nz4x nrkOXowGgsV6wJZ7YUnrHjq3pjiOOxsucwA1hNuNk8B8oj3BVSlLXaoMmuby2Kru NATAxYC1PI5pSJSsJCuuuzMHrDqD6/SDMQ4B7KLMSDvvCVQwqe0rBbquQc+xzsub oB2U8moJ5Kk6CwuTDCgG+6uQPlgzVrBSmQ2qsB372v+mLOwf8UqCmwdNyW0StXnL 7sBgatUpfM9GJg8Hdk/GBNAzj7GRZyUv+H2L2GWAm9IQa9on64xoDTpchkuJJE2J AOD/1auSgcyPEOgvXC9OuQDZKaobpXKWRV+FVjUcMpaTw0rc57gWmijPn+dr/+0J xKUw0dg6uYl14B85eVQPkkNX6WXJLnH1/7ld87gQwtjKS311woW8AvwgAqhQytfW PlxOxkthQWOC04IEWjrVhTKRBBZgarcG8rJijPr8T7rIgOnp9KlTsOW2tZZAixt9 vUvAHxOMNMUiEkzZswTQaVt/y3uW3CigsgCBDqPSGAnqAdko/Sg= =wErf -----END PGP SIGNATURE----- --i0/AhcQY5QxfSsSZ--
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