From owner-svn-src-all@freebsd.org Tue Jan 15 09:48:19 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3D8C61482987; Tue, 15 Jan 2019 09:48:19 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D6474772EA; Tue, 15 Jan 2019 09:48:18 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C7A55191A4; Tue, 15 Jan 2019 09:48:18 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x0F9mIqd001042; Tue, 15 Jan 2019 09:48:18 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x0F9mIIS001041; Tue, 15 Jan 2019 09:48:18 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201901150948.x0F9mIIS001041@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 15 Jan 2019 09:48:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r343042 - head/sys/arm64/arm64 X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: head/sys/arm64/arm64 X-SVN-Commit-Revision: 343042 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: D6474772EA X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.97 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_LONG(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.97)[-0.970,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Jan 2019 09:48:19 -0000 Author: andrew Date: Tue Jan 15 09:48:18 2019 New Revision: 343042 URL: https://svnweb.freebsd.org/changeset/base/343042 Log: Ensure the I-Cache is correctly handled in arm64_icache_sync_range The cache_handle_range macro to handle the arm64 instruction and data cache operations would return when it was complete. This causes problems for arm64_icache_sync_range and arm64_icache_sync_range_checked as they assume they can execute the i-cache handling instruction after it has been called. Fix this by making this assumption correct. While here add missing instruction barriers and adjust the style to match the rest of the assembly. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D18838 Modified: head/sys/arm64/arm64/cpufunc_asm.S Modified: head/sys/arm64/arm64/cpufunc_asm.S ============================================================================== --- head/sys/arm64/arm64/cpufunc_asm.S Tue Jan 15 08:59:51 2019 (r343041) +++ head/sys/arm64/arm64/cpufunc_asm.S Tue Jan 15 09:48:18 2019 (r343042) @@ -77,7 +77,6 @@ __FBSDID("$FreeBSD$"); .if \ic != 0 isb .endif - ret .endm ENTRY(arm64_nullop) @@ -112,6 +111,7 @@ END(arm64_tlb_flushID) */ ENTRY(arm64_dcache_wb_range) cache_handle_range dcop = cvac + ret END(arm64_dcache_wb_range) /* @@ -119,6 +119,7 @@ END(arm64_dcache_wb_range) */ ENTRY(arm64_dcache_wbinv_range) cache_handle_range dcop = civac + ret END(arm64_dcache_wbinv_range) /* @@ -129,6 +130,7 @@ END(arm64_dcache_wbinv_range) */ ENTRY(arm64_dcache_inv_range) cache_handle_range dcop = ivac + ret END(arm64_dcache_inv_range) /* @@ -136,6 +138,7 @@ END(arm64_dcache_inv_range) */ ENTRY(arm64_idcache_wbinv_range) cache_handle_range dcop = civac, ic = 1, icop = ivau + ret END(arm64_idcache_wbinv_range) /* @@ -150,6 +153,8 @@ ENTRY(arm64_icache_sync_range) cache_handle_range dcop = cvau ic ialluis dsb ish + isb + ret END(arm64_icache_sync_range) /* @@ -161,7 +166,8 @@ ENTRY(arm64_icache_sync_range_checked) /* XXX: See comment in arm64_icache_sync_range */ cache_handle_range dcop = cvau ic ialluis - dsb ish + dsb ish + isb SET_FAULT_HANDLER(xzr, x6) mov x0, #0 ret