Date: Mon, 27 Oct 1997 04:01:05 -0800 From: Don Lewis <Don.Lewis@tsc.tdk.com> To: Alexander Litvin <archer@lucky.net>, hackers@FreeBSD.ORG Subject: Re: de0 errors Message-ID: <199710271201.EAA22650@salsa.gv.tsc.tdk.com> In-Reply-To: Alexander Litvin <archer@lucky.net> "Re: de0 errors" (Oct 25, 6:49pm)
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On Oct 25, 6:49pm, Alexander Litvin wrote: } Subject: Re: de0 errors } I experience the same. } } No problem it would be, but with that card the box also seems } to lockup after a while :( It is our proxy server, quite busy } (about 30000 requests per hour), and I don't have opportunity } to investigate it in details, but after installation of DE it } locked up two times during one hour, so I decided to put back } PCI ed. } } All that on 2.2.5, 266MHz P-II, Intel LX chipset. } } > de0 <Digital 21140 Fast Ethernet> rev 18 int a irq 9 on pci0:20 } > de0: SMC 9332DST 21140 [10-100Mb/s] pass 1.2 I don't have information specific to the 440LX chipset, but I suspect that it behaves similarly to the 440FX chipset which is used witht the Pentium Pro. If so, the 9332DST or other 21140 based NIC is probably a bad choice. A 21140A based NIC should work much better. On the PCI bus, there are three flavors of memory read commands. They are MR (Memory Read), which is best for reading small amounts of data, MRL (Memory Read Line), which is best for reading up to the next cache line boundary, and MRM (Memory Read Multiple) which is best for reading multiple cache lines of data in one burst. According to some messages posted to the pci-sig mail list by Bruce Young of Intel, the Intel 430 series chipsets which are used with Pentium processors treat all the flavors of PCI memory reads the same, but the 440FX chipset tries to avoid wasting memory bandwidth by using the PCI memory read command as a hint on whether or not to prefetch more data from memory in preparation for forwarding it to the PCI device. He says the 440FX will disconnect a PCI MR transaction at each cache line boundary, but it generally not do this to to MRL and MRM commands. He also says there is a delay of 8-12 PCI clock cycles at the beginning of PCI memory reads. The information I have says that the 21140 is only capable of issuing MR commands, which means that the data transfer rate across the PCI bus from a 440FX will be pretty bad. The 21140A is capable of issuing both MR and MRM commands, which greatly increases the data transfer rate. You might want to look at http://support.intel.com/oem_developer/chipsets/pci/general/PCI001.HTM
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