Date: Sun, 2 Feb 1997 19:29:32 -0500 From: "David S. Miller" <davem@jenolan.rutgers.edu> To: terry@lambert.org Cc: netdev@roxanne.nuclecu.unam.mx, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702030029.TAA19968@jenolan.caipgeneral> In-Reply-To: <199702030022.RAA09838@phaeton.artisoft.com> (message from Terry Lambert on Sun, 2 Feb 1997 17:22:34 -0700 (MST))
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From: Terry Lambert <terry@lambert.org> Date: Sun, 2 Feb 1997 17:22:34 -0700 (MST) [ CC: list chopped down, all removed are on the lists remaining ;-) ] You are wrong for the BeBox and the SMP PowerMac PPC603 hardware, which are only MEI (no 'S'). I don't know how Intel-centric you are, but I'd just as soon see an entry under SMP, seperate from the CPU architecture, in the build tree. I assume even without the shared cache state they do things reasonably. For example, if 1 asks for a line, and 2 has it but modified he invalidates and then 1 gets the latest copy from that invalidation. I also hope they don't invalidate in this case out to memory, if they do the bus traffic on those boxes must be unpleasant. This is a bad scheme even if 2 gets his copy stright from the others cache even though he himself is pushing straight to ram. ---------------------------------------------//// Yow! 11.26 MB/s remote host TCP bandwidth & //// 199 usec remote TCP latency over 100Mb/s //// ethernet. Beat that! //// -----------------------------------------////__________ o David S. Miller, davem@caip.rutgers.edu /_____________/ / // /_/ ><
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