From owner-freebsd-hackers@FreeBSD.ORG Sun Feb 17 15:41:58 2008 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6CFB116A419 for ; Sun, 17 Feb 2008 15:41:58 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from falcon.cybervisiontech.com (falcon.cybervisiontech.com [217.20.163.9]) by mx1.freebsd.org (Postfix) with ESMTP id E3F3013C455 for ; Sun, 17 Feb 2008 15:41:57 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from localhost (localhost [127.0.0.1]) by falcon.cybervisiontech.com (Postfix) with ESMTP id 86FC343F601 for ; Sun, 17 Feb 2008 17:41:56 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at falcon.cybervisiontech.com Received: from falcon.cybervisiontech.com ([127.0.0.1]) by localhost (falcon.cybervisiontech.com [127.0.0.1]) (amavisd-new, port 10027) with ESMTP id BqORwUrNqEpk for ; Sun, 17 Feb 2008 17:41:56 +0200 (EET) Received: from [10.74.70.239] (unknown [193.138.145.53]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by falcon.cybervisiontech.com (Postfix) with ESMTP id DA46043F600 for ; Sun, 17 Feb 2008 17:41:55 +0200 (EET) Message-ID: <47B855C0.4010703@icyb.net.ua> Date: Sun, 17 Feb 2008 17:41:52 +0200 From: Andriy Gapon User-Agent: Thunderbird 2.0.0.9 (X11/20071208) MIME-Version: 1.0 To: freebsd-hackers@freebsd.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: multiple interrupts between cli and sti X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 17 Feb 2008 15:41:58 -0000 The following question might more relevant to some different mailing list that is not freebsd-specific, but I think my chances are pretty high here too. I read a bunch of docs on x86, on interrupts and a spec of 8259A. And while I think I have a pretty good idea how interrupts work in x86-based system in most case, there is one case that puzzles me. Let's consider the following scenario. Environment: i386 system, 8259A PIC, default interrupt priorities, no auto-eoi. 1. cpu executes cli, from now maskable interrupts are masked 2. an interrupt of lower priority occurs (say irq1) 2.1. 8259A sets the corresponding IRR bit and asserts cpu interrupt line 2.2. cpu goes on with whatever it is doing 3. another interrupt, with higher priority occurs (say irq0) 3.1. 8259A sees that it's a higher priority interrupt, sets another bit in IRR, does some magic on the cpu interrupt line, in the end it is still asserted 3.2. cpu goes on with whatever it is doing 4. cpu executes sti 4.1. interrupts are unmasked 4.2. cpu sees interrupt line status, "conversation" with the PIC takes place 4.3. PIC provides cpu with vector number of pending interrupt request with the highest priority (irq0 in our example), sets ISR bit 4.4. cpu executes interrupt handler through interrupt gate, so interrupts are masked again 4.5. current interrupt handler does its job and signal EOI to PIC, PIC clears the ISR bit 4.6. current interrupt handler finishes via iret unmasking interrupts again And here's what I am fuzzy about. Upon getting EOI for current interrupt PIC should interrupt processor again, so that it serves the second pending interrupt. Am I correct ? How fast does this happen? Is there a window for the processor to return to executing whatever it had before the first interrupt ? I mean, will it be: ... -> iret -> xxx -> xxx -> interrupted again or ... -> iret -> interrupted again Is this a deterministic behavior ? Or some timings are at play? Thank you in advance. I hope this was not a too trivial or too boring question :-) -- Andriy Gapon