From owner-svn-src-stable@freebsd.org Thu Mar 2 04:55:55 2017 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E8FFECF5CA8; Thu, 2 Mar 2017 04:55:55 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B5675CCC; Thu, 2 Mar 2017 04:55:55 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v224tsHQ099009; Thu, 2 Mar 2017 04:55:54 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v224tstC099008; Thu, 2 Mar 2017 04:55:54 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201703020455.v224tstC099008@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Thu, 2 Mar 2017 04:55:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r314540 - stable/11/sys/arm/freescale/imx X-SVN-Group: stable-11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Mar 2017 04:55:56 -0000 Author: ian Date: Thu Mar 2 04:55:54 2017 New Revision: 314540 URL: https://svnweb.freebsd.org/changeset/base/314540 Log: MFC r312679: Handle imx6 erratum ERR004346... to reboot, clear the SRS bit twice within the same cycle of the 32khz clock. I've never actually noticed this error happening, but it's an easy fix. Modified: stable/11/sys/arm/freescale/imx/imx_machdep.c Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/arm/freescale/imx/imx_machdep.c ============================================================================== --- stable/11/sys/arm/freescale/imx/imx_machdep.c Thu Mar 2 04:42:33 2017 (r314539) +++ stable/11/sys/arm/freescale/imx/imx_machdep.c Thu Mar 2 04:55:54 2017 (r314540) @@ -69,11 +69,18 @@ imx_wdog_cpu_reset(vm_offset_t wdcr_phys * Trigger an immediate reset by clearing the SRS bit in the watchdog * control register. The reset happens on the next cycle of the wdog * 32KHz clock, so hang out in a spin loop until the reset takes effect. + * + * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice + * within the same cycle of the 32khz clock to reliably trigger the + * reset. Writing it 3 times in a row ensures at least 2 of the writes + * happen in the same 32k clock cycle. */ if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) { printf("cpu_reset() can't find its control register... locking up now."); } else { *pcr &= ~WDOG_CR_SRS; + *pcr &= ~WDOG_CR_SRS; + *pcr &= ~WDOG_CR_SRS; } for (;;) continue;