From owner-svn-soc-all@FreeBSD.ORG Sun Jun 22 21:04:15 2014 Return-Path: Delivered-To: svn-soc-all@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 32FAAD39 for ; Sun, 22 Jun 2014 21:04:15 +0000 (UTC) Received: from socsvn.freebsd.org (socsvn.freebsd.org [IPv6:2001:1900:2254:206a::50:2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 053E325F5 for ; Sun, 22 Jun 2014 21:04:15 +0000 (UTC) Received: from socsvn.freebsd.org ([127.0.1.124]) by socsvn.freebsd.org (8.14.8/8.14.8) with ESMTP id s5ML4EJ5023808 for ; Sun, 22 Jun 2014 21:04:14 GMT (envelope-from astarasikov@FreeBSD.org) Received: (from www@localhost) by socsvn.freebsd.org (8.14.8/8.14.8/Submit) id s5ML4E8U023590 for svn-soc-all@FreeBSD.org; Sun, 22 Jun 2014 21:04:14 GMT (envelope-from astarasikov@FreeBSD.org) Date: Sun, 22 Jun 2014 21:04:14 GMT Message-Id: <201406222104.s5ML4E8U023590@socsvn.freebsd.org> X-Authentication-Warning: socsvn.freebsd.org: www set sender to astarasikov@FreeBSD.org using -f From: astarasikov@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r269884 - in soc2014/astarasikov/head/sys/arm: arm include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 Jun 2014 21:04:15 -0000 Author: astarasikov Date: Sun Jun 22 21:04:13 2014 New Revision: 269884 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=269884 Log: arm: do not use performance counters in QEMU Currently Android Emulator and older versions of QEMU will trap if performance counters are accessed via CP15. This patch provides a workaround for it. Modified: soc2014/astarasikov/head/sys/arm/arm/cpufunc.c soc2014/astarasikov/head/sys/arm/include/cpu.h Modified: soc2014/astarasikov/head/sys/arm/arm/cpufunc.c ============================================================================== --- soc2014/astarasikov/head/sys/arm/arm/cpufunc.c Sun Jun 22 21:03:09 2014 (r269883) +++ soc2014/astarasikov/head/sys/arm/arm/cpufunc.c Sun Jun 22 21:04:13 2014 (r269884) @@ -1405,6 +1405,9 @@ static __inline void cpu_scc_setup_ccnt(void) { +#if defined(QEMU_WORKAROUNDS) + return; +#else /* This is how you give userland access to the CCNT and PMCn * registers. * BEWARE! This gives write access also, which may not be what @@ -1427,6 +1430,7 @@ : "r"(0xFFFFFFFF), "r"(0x00000005), "r"(0x80000000)); +#endif } #endif Modified: soc2014/astarasikov/head/sys/arm/include/cpu.h ============================================================================== --- soc2014/astarasikov/head/sys/arm/include/cpu.h Sun Jun 22 21:03:09 2014 (r269883) +++ soc2014/astarasikov/head/sys/arm/include/cpu.h Sun Jun 22 21:04:13 2014 (r269884) @@ -15,9 +15,15 @@ get_cyclecount(void) { /* This '#if' asks the question 'Does CP15/SCC include performance counters?' */ -#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \ + +/* QEMU has got support for emulating performance counters + * around march 2014. Android Emulator is lagging behind and will + * die with 'unimplemented cp15 register read' trap. + * Maybe one day we can revert QEMU_WORKAROUNDS */ +#if (defined(CPU_ARM1136) || defined(CPU_ARM1176) \ || defined(CPU_MV_PJ4B) \ - || defined(CPU_CORTEXA) || defined(CPU_KRAIT) + || defined(CPU_CORTEXA) || defined(CPU_KRAIT)) \ + && !defined(QEMU_WORKAROUNDS) uint32_t ccnt; uint64_t ccnt64;