From owner-svn-src-projects@FreeBSD.ORG Sat May 23 18:00:20 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 56E36106567B; Sat, 23 May 2009 18:00:20 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 449E68FC1B; Sat, 23 May 2009 18:00:20 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n4NI0KUK062765; Sat, 23 May 2009 18:00:20 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n4NI0KXi062764; Sat, 23 May 2009 18:00:20 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200905231800.n4NI0KXi062764@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Sat, 23 May 2009 18:00:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r192655 - projects/mips/sys/mips/mips X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 May 2009 18:00:20 -0000 Author: gonzo Date: Sat May 23 18:00:20 2009 New Revision: 192655 URL: http://svn.freebsd.org/changeset/base/192655 Log: - Remove stale comments - Replace a1 with k1 to while restoring context. a1 was there by mistake, interrupts are disabled at this point and it's safe to use k0, k1. This code never was reached beacasue current Status register handling prevented interrupta from user mode. Modified: projects/mips/sys/mips/mips/exception.S Modified: projects/mips/sys/mips/mips/exception.S ============================================================================== --- projects/mips/sys/mips/mips/exception.S Sat May 23 17:17:54 2009 (r192654) +++ projects/mips/sys/mips/mips/exception.S Sat May 23 18:00:20 2009 (r192655) @@ -689,36 +689,27 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE /* * Call the interrupt handler. */ + break la k0, _C_LABEL(cpu_intr) jalr k0 sw a3, STAND_RA_OFFSET(sp) # for debugging + /* - * Since interrupts are enabled at this point, we use a1 instead of - * k0 or k1 to store the PCB pointer. This is because k0 and k1 - * are not preserved across interrupts. ** RRS - And how did the - * get enabled? cpu_intr clears the cause register but it does - * not touch the sr as far as I can see thus intr are still - * disabled. + * DO_AST enabled interrupts */ DO_AST /* - * Restore user registers and return. NOTE: interrupts are enabled. - */ - -/* - * Since interrupts are enabled at this point, we use a1 instead of - * k0 or k1 to store the PCB pointer. This is because k0 and k1 - * are not preserved across interrupts. + * Restore user registers and return. */ - mtc0 zero, COP_0_STATUS_REG + mtc0 zero, COP_0_STATUS_REG # re-disable interrupts ITLBNOPFIX li v0, SR_EXL mtc0 v0, COP_0_STATUS_REG # set exeption level bit. ITLBNOPFIX GET_CPU_PCPU(k1) - lw a1, PC_CURPCB(k1) + lw k1, PC_CURPCB(k1) RESTORE_U_PCB_REG(s0, S0, k1) RESTORE_U_PCB_REG(s1, S1, k1) RESTORE_U_PCB_REG(s2, S2, k1)