From owner-freebsd-hackers@FreeBSD.ORG Sat Mar 28 15:40:36 2015 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 007CA5D5; Sat, 28 Mar 2015 15:40:35 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id AD867188; Sat, 28 Mar 2015 15:40:35 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.84 (FreeBSD)) (envelope-from ) id 1Ybsqe-000Kmu-0Y; Sat, 28 Mar 2015 18:40:32 +0300 Date: Sat, 28 Mar 2015 18:40:31 +0300 From: Slawa Olhovchenkov To: Adrian Chadd Subject: Re: irq cpu binding Message-ID: <20150328154031.GA23643@zxy.spb.ru> References: <20150328112035.GZ23643@zxy.spb.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false Cc: "freebsd-hackers@freebsd.org" X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Mar 2015 15:40:36 -0000 On Sat, Mar 28, 2015 at 08:20:08AM -0700, Adrian Chadd wrote: > On 28 March 2015 at 04:20, Slawa Olhovchenkov wrote: > > Can someone describe how on FreeBSD/amd64 do interrupt handling? > > Can be interrupt handler (hardware interrupt) direct dispatch to > > specific CPU core (and only to this core)? > > Can be all work be only on this core (ithread, device driver interrupt > > handler, finalise)? > > Yes - you can use cpuset on the interrupt to get them bound that way. > > John and I are trying to make that whole process more automated and > NUMA friendly. I'm debugging some of his work at the moment. cpuset don't work as expected -- I see irq handling on other cpu.