Date: Mon, 02 Sep 1996 19:26:16 -0600 From: Steve Passe <smp@csn.net> To: erich@uruk.org Cc: terry@lambert.org, freebsd-smp@freebsd.org, rv@groa.uct.ac.za Subject: Re: SMP on Intel MG15 Message-ID: <199609030126.TAA08511@clem.systemsix.com> In-Reply-To: Your message of "Mon, 02 Sep 1996 17:56:49 PDT." <199609030056.RAA19083@uruk.org>
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Hi,
>[The messages are flying pretty fast on this thread... I can barely keep
up ;-)]
i spent most of the day emailing someone or another. but, after a week of
almost no progress we have gotten quite far.
>It does ignore the following STARTUP IPI completely.
>
>The Intel CPUs only pay attention to the first STARTUP IPI after a reset
>(I can't remember where this is documented, but I've both seen it and
>talked with a few of the hardware geeks who implemented it in the first
>place).
spec 1.4, B.4.2 says:
only one time after RESET or after an INIT IPI reception or pin assertion
^^^^^^^^^^^^^
( I assume this means there is a hardware equivilant pin for INIT IPI)
it is because of this line that I assummed the INIT IPI was for getting the
2nd CPU into a state ready for the following STARTUP IPI, and not to
actually launch the bootstrap code.
>I've read the 1.4 document pretty carefully. In my experience it doesn't
>contradict itself, but it is somewhat ambiguous in a few spots. If you
>have some real problems, I can probably dredge up my connections at Intel
>and get the complaints to them.
page B3, example B.1 "Universal Startr-up Algorithm":
shows 2 STARTUP IPIs being run in a row
this contradits the above "one time" rule.
>Yes, as I mentioned before:
>
> -- FreeBSD-SMP presumes the boot CPU is APIC id #0, and the second CPU
> is APIC id #1. Yes, there are several tables where the APIC id is
> used as an index.
I'm chasing those down now...
--
Steve Passe | powered by
smp@csn.net | FreeBSD
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