From owner-freebsd-arm@FreeBSD.ORG Fri Mar 20 05:35:52 2015 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 27888232 for ; Fri, 20 Mar 2015 05:35:52 +0000 (UTC) Received: from feith1.FEITH.COM (feith1.FEITH.COM [192.251.93.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id DFA7D261 for ; Fri, 20 Mar 2015 05:35:51 +0000 (UTC) Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.9+Sun/8.12.9) with ESMTP id t2K5ZUdh023593 for ; Fri, 20 Mar 2015 01:35:30 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.9+Sun/8.14.9) with ESMTP id t2K5ZUjD011381 for ; Fri, 20 Mar 2015 01:35:30 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.9+Sun/8.14.9/Submit) id t2K5ZQdo011380 for freebsd-arm@freebsd.org; Fri, 20 Mar 2015 01:35:26 -0400 (EDT) Date: Fri, 20 Mar 2015 01:35:26 -0400 (EDT) From: John Wehle Message-Id: <201503200535.t2K5ZQdo011380@jwlab.FEITH.COM> To: freebsd-arm@freebsd.org Subject: current meaning of BUS_DMA_COHERENT MIME-Version: 1.0 Content-Type: text/plain X-DCC--Metrics: feith1; whitelist X-Scanned-By: MIMEDefang 2.67 on 192.251.93.1 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Mar 2015 05:35:52 -0000 The bus_dmamap_create manual page says: Attempt to map the memory loaded with this map such that cache sync operations are as cheap as possible. ... Use of this flag does not remove the requirement of using bus_dmamap_sync() However busdma_machdep-v6.c for ARM has the comment: * Create a cache of buffers in uncacheable memory, to implement the * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag. Is the manual page out of date? Does FreeBSD now guarentee that memory allocated by bus_dmamem_alloc using BUS_DMA_COHERENT doesn't require bus_dmamap_sync operations? Part of my concern is that there appears to be existing FreeBSD device driver code that assumes BUS_DMA_COHERENT means uncacheable memory (i.e. bus_dmamap_sync is unnecessary) which I thought was indicated by BUS_DMA_NOCACHE, not BUS_DMA_COHERENT. -- John