From owner-freebsd-hardware Fri Jan 9 14:46:00 1998 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id OAA21232 for hardware-outgoing; Fri, 9 Jan 1998 14:46:00 -0800 (PST) (envelope-from owner-freebsd-hardware) Received: from allegro.lemis.com (allegro.lemis.com [192.109.197.134]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id OAA21216 for ; Fri, 9 Jan 1998 14:45:50 -0800 (PST) (envelope-from grog@lemis.com) Received: from freebie.lemis.com (freebie.lemis.com [192.109.197.137]) by allegro.lemis.com (8.8.7/8.8.5) with ESMTP id JAA01220; Sat, 10 Jan 1998 09:15:39 +1030 (CST) Received: (from grog@localhost) by freebie.lemis.com (8.8.8/8.8.7) id JAA12185; Sat, 10 Jan 1998 09:15:39 +1030 (CST) (envelope-from grog) Message-ID: <19980110091539.04276@lemis.com> Date: Sat, 10 Jan 1998 09:15:39 +1030 From: Greg Lehey To: Mike Smith Cc: hardware@FreeBSD.ORG Subject: Re: LS-120, Riva 128, ASUS motherboard References: <19980109194006.42229@lemis.com> <199801091231.XAA00367@word.smith.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.84e In-Reply-To: <199801091231.XAA00367@word.smith.net.au>; from Mike Smith on Fri, Jan 09, 1998 at 11:01:19PM +1030 Organisation: LEMIS, PO Box 460, Echunga SA 5153, Australia Phone: +61-8-8388-8286 Fax: +61-8-8388-8725 Mobile: +61-41-739-7062 WWW-Home-Page: http://www.lemis.com/~grog Sender: owner-freebsd-hardware@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk On Fri, Jan 09, 1998 at 11:01:19PM +1030, Mike Smith wrote: >> Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. >> Extract: >> >> The Intel 430TX PCIset (430TX) consists of the 82439TX System >> Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator >> (PIIX4). [...] The MTXC integrates the cache and main memory DRAM >> control functions and provides bus control to transfers between the >> CPU, cache, main memory, and the PCI Bus. The second level (L2) >> cache controller supports a writeback cache policy for cache sizes >> of 256 Kbytes and 512 Kbytes. >> >> I'm downloading the document, and will print it out, but this >> certainly doesn't sound like Tom's Hardware Guide. > > As is typical, reading the datasheets tends to give better and more > believable answers than what is really the computing equivalent of a > revhead's magazine. Of course, lightly editorial dreck is easier on > the eyes when it comes to reading... Well, in fact, it pays to read the web page more carefully. The text I quote is completely correct, but it doesn't say what I assumed. I see that nobody else noticed this either: The second level (L2) cache controller supports a writeback cache policy for cache sizes of 256 Kbytes and 512 Kbytes. *Kilo*bytes. Cache, not cacheable memory space. Of course I read the data sheet, like I said I would. It requires a tag RAM for all cache configurations. It says that there's no L2 cache above 64 MB. It may be that it's possible to work around this, but I'm sure that any mother board which did would advertise the fact. Anybody want to buy a TX motherboard? Greg