From owner-svn-src-head@FreeBSD.ORG Sun Mar 1 20:32:36 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 62CE7466; Sun, 1 Mar 2015 20:32:36 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 3312DFE3; Sun, 1 Mar 2015 20:32:36 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t21KWaq5061144; Sun, 1 Mar 2015 20:32:36 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t21KWaCm061143; Sun, 1 Mar 2015 20:32:36 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201503012032.t21KWaCm061143@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sun, 1 Mar 2015 20:32:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279492 - head/sys/dev/etherswitch/arswitch X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Mar 2015 20:32:36 -0000 Author: adrian Date: Sun Mar 1 20:32:35 2015 New Revision: 279492 URL: https://svnweb.freebsd.org/changeset/base/279492 Log: AR8327: Disable energy-efficient ethernet support in the PHYs. I noticed that openwrt/linux does this, citing "instability", so until they figure out why I'm going to disable it here as well. Tested: * QCA AP135 - QCA955x SoC + AR8327 switch. Modified: head/sys/dev/etherswitch/arswitch/arswitch_8327.c Modified: head/sys/dev/etherswitch/arswitch/arswitch_8327.c ============================================================================== --- head/sys/dev/etherswitch/arswitch/arswitch_8327.c Sun Mar 1 20:26:03 2015 (r279491) +++ head/sys/dev/etherswitch/arswitch/arswitch_8327.c Sun Mar 1 20:32:35 2015 (r279492) @@ -66,7 +66,11 @@ static void ar8327_phy_fixup(struct arswitch_softc *sc, int phy) { - + if (bootverbose) + device_printf(sc->sc_dev, + "%s: called; phy=%d; chiprev=%d\n", __func__, + phy, + sc->chip_rev); switch (sc->chip_rev) { case 1: /* For 100M waveform */ @@ -385,23 +389,23 @@ ar8327_fetch_pdata_pad(struct arswitch_s sbuf, &val) == 0) pc->pipe_rxclk_sel = val; -#if 0 - device_printf(sc->sc_dev, - "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, " - "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, " - "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n", - __func__, - pad, - pc->mode, - pc->rxclk_sel, - pc->txclk_sel, - pc->txclk_delay_sel, - pc->rxclk_delay_sel, - pc->txclk_delay_en, - pc->rxclk_delay_en, - pc->sgmii_delay_en, - pc->pipe_rxclk_sel); -#endif + if (bootverbose) { + device_printf(sc->sc_dev, + "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, " + "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, " + "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n", + __func__, + pad, + pc->mode, + pc->rxclk_sel, + pc->txclk_sel, + pc->txclk_delay_sel, + pc->rxclk_delay_sel, + pc->txclk_delay_en, + pc->rxclk_delay_en, + pc->sgmii_delay_en, + pc->pipe_rxclk_sel); + } return (1); } @@ -637,6 +641,15 @@ ar8327_hw_global_setup(struct arswitch_s arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB, AR8327_MODULE_EN_MIB); + /* Disable EEE on all ports due to stability issues */ + t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL); + t |= AR8327_EEE_CTRL_DISABLE_PHY(0) | + AR8327_EEE_CTRL_DISABLE_PHY(1) | + AR8327_EEE_CTRL_DISABLE_PHY(2) | + AR8327_EEE_CTRL_DISABLE_PHY(3) | + AR8327_EEE_CTRL_DISABLE_PHY(4); + arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t); + /* Set the right number of ports */ sc->info.es_nports = 6;