From owner-svn-src-all@FreeBSD.ORG Tue Mar 16 17:45:17 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 12EFD106564A; Tue, 16 Mar 2010 17:45:17 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 024768FC12; Tue, 16 Mar 2010 17:45:17 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o2GHjGqQ051632; Tue, 16 Mar 2010 17:45:16 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o2GHjG3G051630; Tue, 16 Mar 2010 17:45:16 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201003161745.o2GHjG3G051630@svn.freebsd.org> From: Pyun YongHyeon Date: Tue, 16 Mar 2010 17:45:16 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r205221 - head/sys/dev/bge X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Mar 2010 17:45:17 -0000 Author: yongari Date: Tue Mar 16 17:45:16 2010 New Revision: 205221 URL: http://svn.freebsd.org/changeset/base/205221 Log: Revert r205090. It's hard to know when the mail box register write will get flushed to the hardware and it may take longer. Pointed out by: scottl Modified: head/sys/dev/bge/if_bge.c Modified: head/sys/dev/bge/if_bge.c ============================================================================== --- head/sys/dev/bge/if_bge.c Tue Mar 16 16:55:12 2010 (r205220) +++ head/sys/dev/bge/if_bge.c Tue Mar 16 17:45:16 2010 (r205221) @@ -3654,22 +3654,6 @@ bge_intr(void *xsc) #endif /* - * Do the mandatory PCI flush as well as get the link status. - */ - statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; - - /* Make sure the descriptor ring indexes are coherent. */ - bus_dmamap_sync(sc->bge_cdata.bge_status_tag, - sc->bge_cdata.bge_status_map, - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; - tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; - sc->bge_ldata.bge_status_block->bge_status = 0; - bus_dmamap_sync(sc->bge_cdata.bge_status_tag, - sc->bge_cdata.bge_status_map, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - /* * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't * disable interrupts by writing nonzero like we used to, since with * our current organization this just gives complications and @@ -3691,6 +3675,22 @@ bge_intr(void *xsc) */ bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); + /* + * Do the mandatory PCI flush as well as get the link status. + */ + statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; + + /* Make sure the descriptor ring indexes are coherent. */ + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; + tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; + sc->bge_ldata.bge_status_block->bge_status = 0; + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || statusword || sc->bge_link_evt)