Date: Sat, 29 Jul 2023 06:39:36 GMT From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org Subject: git: 3a3bceadc7f3 - main - cad/yosys-systemverilog: Broken Message-ID: <202307290639.36T6daEg001746@gitrepo.freebsd.org>
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The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4 commit 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4 Author: Yuri Victorovich <yuri@FreeBSD.org> AuthorDate: 2023-07-29 06:39:15 +0000 Commit: Yuri Victorovich <yuri@FreeBSD.org> CommitDate: 2023-07-29 06:39:15 +0000 cad/yosys-systemverilog: Broken Reported by: fallout --- cad/yosys-systemverilog/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile index 8918269008c0..f7b6e2d8c631 100644 --- a/cad/yosys-systemverilog/Makefile +++ b/cad/yosys-systemverilog/Makefile @@ -10,6 +10,8 @@ WWW= https://github.com/antmicro/yosys-systemverilog LICENSE= APACHE20 LICENSE_FILE= ${WRKSRC}/LICENSE +BROKEN= incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845 + BUILD_DEPENDS= bash:shells/bash \ yosys>0:cad/yosys LIB_DEPENDS= libcapnp.so:devel/capnproto \
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