Date: Sat, 18 Apr 1998 23:57:38 +0200 (MET DST) From: Wolfgang Helbig <helbig@Informatik.BA-Stuttgart.DE> To: hm@hcs.de Cc: FreeBSD-ISDN@FreeBSD.ORG (FreeBSD ISDN mailinglist) Subject: Re: first ICMP reply Message-ID: <199804182157.XAA01345@rvc1.informatik.ba-stuttgart.de> In-Reply-To: <m0yO0t1-0000bTC@hcswork.hcs.de> from Hellmuth Michaelis at "Apr 11, 98 04:04:03 pm"
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> >From the keyboard of Wolfgang Helbig:
>
> > For whatever reason, if doing a ping -c1 via a raw IP interface,
> > the ICMP reply is not received.
>
> I do receive a reply with a ping -c1 and 0.51. And i'd like to know
> the reason why you don't ;-)
So did I. It only happened with the CREATIX-Card (IOM-1, HSCX is
SAB 82525N) The transmit FIFO turned out not to be ready, even if
the XPF-interrupt is indicated, as opposed to the specs. The following
diff against i4b-00.51 is a workaround for this:
This patch also unifies some more IOM-1 and IOM-2 HSCX-init and again
includes the FreeBSD-current ,,time changes''.
But the really important part is the new line
isic_hscx_waitxfw(sc, h_chan);
just before
HSCX_WRFIFO(h_chan, chan->out_mbuf_cur_ptr, nextlen);
in isic_hscx_irq().
I measured up to 2 ms waiting time in isic_hscx_waitx.
Wolfgang
--- /home/helbig/src/i4b/layer1/i4b_hscx.c Thu Mar 12 10:38:52 1998
+++ layer1/i4b_hscx.c Sat Apr 18 22:48:12 1998
@@ -214,7 +214,11 @@
hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
hdr.dir = FROM_NT;
hdr.count = ++sc->sc_trace_bcount;
+#if defined(__FreeBSD__) && __FreeBSD__ >= 3
+ getmicrotime(&hdr.time);
+#else
hdr.time = time;
+#endif
MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
}
@@ -288,7 +292,11 @@
hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
hdr.dir = FROM_NT;
hdr.count = ++sc->sc_trace_bcount;
+#if defined(__FreeBSD__) && __FreeBSD__ >= 3
+ getmicrotime(&hdr.time);
+#else
hdr.time = time;
+#endif
MPH_Trace_Ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
}
@@ -371,7 +379,11 @@
hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_bcount;
+#if defined(__FreeBSD__) && __FreeBSD__ >= 3
+ getmicrotime(&hdr.time);
+#else
hdr.time = time;
+#endif
MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
}
@@ -391,7 +403,6 @@
while(chan->out_mbuf_cur && len != HSCX_FIFO_LEN)
{
- DBGL1(L1_H_IRQ, "isic_hscx_irq", ("out_mbuf_cur_len: %d\n", chan->out_mbuf_cur_len));
nextlen = min(chan->out_mbuf_cur_len, HSCX_FIFO_LEN - len);
#ifdef NOTDEF
@@ -404,6 +415,7 @@
next_len);
#endif
+ isic_hscx_waitxfw(sc, h_chan);
HSCX_WRFIFO(h_chan, chan->out_mbuf_cur_ptr, nextlen);
cmd |= HSCX_CMDR_XTF;
@@ -427,7 +439,11 @@
hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_bcount;
+#if defined(__FreeBSD__) && __FreeBSD__ >= 3
+ getmicrotime(&hdr.time);
+#else
hdr.time = time;
+#endif
MPH_Trace_Ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
}
}
@@ -474,14 +490,6 @@
HSCX_CCR1_CM2 | /* clock mode 5 */
HSCX_CCR1_CM0);
- /* XAD1: Transmit Address Byte 1 */
- HSCX_WRITE(h_chan, H_XAD1, 0xff); /* fully transparent setup */
-
- /* XAD2: Transmit Address Byte 2 */
- HSCX_WRITE(h_chan, H_XAD2, 0xff); /* fully transparent setup */
-
- /* RAH2: Receive Address Byte High Reg. 2 */
- HSCX_WRITE(h_chan, H_RAH2, 0xff); /* fully transparent setup */
/* XBCH: reset Transmit Byte Count High */
HSCX_WRITE(h_chan, H_XBCH, 0x00);
@@ -550,8 +558,6 @@
}
else /* IOM 1 setup */
{
- /* MASK */
- HSCX_WRITE(h_chan, H_MASK, 0xff);
/* CCR1: Power Up, Clock Mode 1 */
HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU | /* power up */
@@ -585,9 +591,6 @@
/* Raw Telephony, extended transparent mode 1 */
/* fully transparent, no framing, bitstuffing, CRC */
- HSCX_WRITE(h_chan, H_XAD1, 0xff); /* XAD1 */
- HSCX_WRITE(h_chan, H_XAD2, 0xff); /* XAD2 */
- HSCX_WRITE(h_chan, H_RAH2, 0xff); /* RAH2 */
HSCX_WRITE(h_chan, H_MODE, HSCX_MODE_MDS1|HSCX_MODE_MDS0|HSCX_MODE_ADM|HSCX_MODE_RTS);
HSCX_WRITE(h_chan, H_CCR1, HSCX_CCR1_PU|HSCX_CCR1_CM0); /* CCR1 */
}
@@ -595,6 +598,15 @@
/* common IOM-1 and IOM-2 setup */
+ /* XAD1: Transmit Address Byte 1 */
+ HSCX_WRITE(h_chan, H_XAD1, 0xff); /* fully transparent setup */
+
+ /* XAD2: Transmit Address Byte 2 */
+ HSCX_WRITE(h_chan, H_XAD2, 0xff); /* fully transparent setup */
+
+ /* RAH2: Receive Address Byte High Reg. 2 */
+ HSCX_WRITE(h_chan, H_RAH2, 0xff); /* fully transparent setup */
+
isic_hscx_cmd(sc, h_chan, HSCX_CMDR_RHR|HSCX_CMDR_XRES);
/* don't touch ICA, EXA and EXB bits, this could be HSCX_CH_B */
@@ -685,7 +697,8 @@
if(timeout == 0)
{
DBGL1(L1_H_ERR, "isic_hscx_waitxfw", ("HSCX wait for XFW timeout!\n"))
- }
+ } else if (timeout != 200)
+ DBGL1(L1_H_ERR, "isic_hscx_waitxfw", ("timeout: %d\n", timeout))
}
#endif /* NISIC > 0 */
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