From owner-svn-src-head@FreeBSD.ORG Wed Nov 20 15:53:50 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id BDB60A21; Wed, 20 Nov 2013 15:53:50 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id ADCE824D7; Wed, 20 Nov 2013 15:53:50 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rAKFroK2057979; Wed, 20 Nov 2013 15:53:50 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id rAKFroGX057978; Wed, 20 Nov 2013 15:53:50 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201311201553.rAKFroGX057978@svn.freebsd.org> From: Ian Lepore Date: Wed, 20 Nov 2013 15:53:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r258392 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Nov 2013 15:53:50 -0000 Author: ian Date: Wed Nov 20 15:53:50 2013 New Revision: 258392 URL: http://svnweb.freebsd.org/changeset/base/258392 Log: Call cpu_setup() immediately after the page tables are installed. This enables data cache and other chip-specific features. It was previously done via an early SYSINIT, but it was being done after pmap and vm setup, and those setups need to use mutexes. On some modern ARM platforms, the ldrex/strex instructions that implement mutexes require the data cache to be enabled. A nice side effect of enabling caching earlier is that it eliminates the multi-second pause that used to happen early in boot while physical memory and pmap and vm were being set up. On boards with 1 GB or more of ram this pause was very noticible, sometimes 5-6 seconds. PR: arm/183740 Modified: head/sys/arm/arm/machdep.c Modified: head/sys/arm/arm/machdep.c ============================================================================== --- head/sys/arm/arm/machdep.c Wed Nov 20 13:22:22 2013 (r258391) +++ head/sys/arm/arm/machdep.c Wed Nov 20 15:53:50 2013 (r258392) @@ -361,7 +361,6 @@ cpu_startup(void *dummy) #endif #endif - cpu_setup(""); identify_arm_cpu(); printf("real memory = %ju (%ju MB)\n", (uintmax_t)ptoa(physmem), @@ -1431,6 +1430,12 @@ initarm(struct arm_boot_params *abp) cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); /* + * Now that proper page tables are installed, call cpu_setup() to enable + * instruction and data caches and other chip-specific features. + */ + cpu_setup(""); + + /* * Only after the SOC registers block is mapped we can perform device * tree fixups, as they may attempt to read parameters from hardware. */