Date: Mon, 2 Oct 2017 19:10:35 -0700 From: Mark Millard <markmi@dsl-only.net> To: andrew@freebsd.org, svn-src-head@freebsd.org, freebsd-arm <freebsd-arm@freebsd.org> Subject: Re: svn commit: r324207 - head/sys/arm64/arm64 Message-ID: <E261FC07-3387-42B6-B8B4-EA4DE657D8A8@dsl-only.net>
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> Author: andrew > Date: Mon Oct 2 14:22:35 2017 > New Revision: 324207 > URL:=20 > https://svnweb.freebsd.org/changeset/base/324207 >=20 >=20 > Log: > Add a memory barrier to ensure the atomic write is visible to the = other > CPUs before waking them up. > =20 > Sponsored by: DARPA, AFRL >=20 > Modified: > head/sys/arm64/arm64/mp_machdep.c >=20 > Modified: head/sys/arm64/arm64/mp_machdep.c > = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D > --- head/sys/arm64/arm64/mp_machdep.c Mon Oct 2 14:19:31 2017 = (r324206) > +++ head/sys/arm64/arm64/mp_machdep.c Mon Oct 2 14:22:35 2017 = (r324207) > @@ -236,7 +236,10 @@ release_aps(void *dummy __unused) > =20 > atomic_store_rel_int(&aps_ready, 1); > /* Wake up the other CPUs */ > - __asm __volatile("sev"); > + __asm __volatile( > + "dsb ishst \n" > + "sev \n" > + ::: "memory"); > =20 > printf("Release APs\n"); There is another sev instruction without a prior memory barrier: Index: /usr/src/sys/arm64/arm64/identcpu.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- /usr/src/sys/arm64/arm64/identcpu.c (revision 323676) +++ /usr/src/sys/arm64/arm64/identcpu.c (working copy) @@ -1109,6 +1109,9 @@ =20 /* Wake up the other CPUs */ atomic_store_rel_int(&ident_lock, 0); - __asm __volatile("sev" ::: "memory"); + __asm __volatile( + "dsb ish \n" + "sev \n" + ::: "memory"); } } (No claim that the dsb form is optimal. Arm documentation says that they recommend every sev be preceded by a dsb and I picked ish to experiment with.) See comments and extra attachment in bugzilla 222234 (which you have fixed with your change). [Specifically your change should make non-debug kernels boot Pine64+ 2GB's again. (I had used just "dsb ish" get get such to boot.)] =3D=3D=3D Mark Millard markmi at dsl-only.net
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