From owner-p4-projects@FreeBSD.ORG Wed Dec 5 21:27:06 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 0502F24E; Wed, 5 Dec 2012 21:27:06 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 9FD1E24C for ; Wed, 5 Dec 2012 21:27:05 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 8083F8FC08 for ; Wed, 5 Dec 2012 21:27:05 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.5/8.14.5) with ESMTP id qB5LR5Ww086084 for ; Wed, 5 Dec 2012 21:27:05 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.5/8.14.5/Submit) id qB5LR5nh086081 for perforce@freebsd.org; Wed, 5 Dec 2012 21:27:05 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Wed, 5 Dec 2012 21:27:05 GMT Message-Id: <201212052127.qB5LR5nh086081@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson Subject: PERFORCE change 219888 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.14 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Dec 2012 21:27:06 -0000 http://p4web.freebsd.org/@@219888?ac=10 Change 219888 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2012/12/05 21:26:57 Update CHERI assembly code for storing and loading data via capabilities, following an assembler update. Immediates are now supported. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#15 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#15 (text+ko) ==== @@ -167,64 +167,62 @@ * XXXRW: immediates not yet supported by the assembler. */ #define CHERI_CSB(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csb %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csb %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSH(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csh %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csh %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSW(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csw %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csw %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CSD(rs, rt, offset, cb) do { \ - __asm__ __volatile__ ("csd %0, %1($c%2)" : : \ - "r" (rs), "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("csd %0, %1, %2($c%3)" : : \ + "r" (rs), "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) /* * Data loads: while these don't much with c0, they do require memory * clobbers. - * - * XXXRW: immediates not yet supported by the assembler. */ #define CHERI_CLB(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clb %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clb %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset),"i" (cb) : "memory"); \ } while (0) #define CHERI_CLH(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clh %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clh %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLW(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clw %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clw %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLD(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("cld %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("cld %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLBU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clbu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clbu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLHU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clhu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clhu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) #define CHERI_CLWU(rd, rt, offset, cb) do { \ - __asm__ __volatile__ ("clwu %0, %1($c%2)" : \ - "=r" (rd) : "r" (rt), "i" (cb) : "memory"); \ + __asm__ __volatile__ ("clwu %0, %1, %2($c%3)" : \ + "=r" (rd) : "r" (rt), "i" (offset), "i" (cb) : "memory"); \ } while (0) /*