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From: "Randall R. Stewart" <rrs@FreeBSD.org>
To: Perforce Change Reviews <perforce@freebsd.org>
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Subject: PERFORCE change 136804 for review
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http://perforce.freebsd.org/chv.cgi?CH=136804

Change 136804 by rrs@rrs-mips2-jnpr on 2008/03/04 11:33:41

	PG_XXX -> PTE_XXX

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#8 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#8 (text+ko) ====

@@ -280,7 +280,7 @@
 	mfc0	v1, COP_0_STATUS_REG		# Save the status register.
 	mtc0	zero, COP_0_STATUS_REG		# Disable interrupts
 	ITLBNOPFIX
-	li	v0, (PG_HVPN | PG_ASID)
+	li	v0, (PTE_HVPN | PTE_ASID)
 	and	a0, a0, v0			# Make shure valid hi value.
 	_MFC0	t0, COP_0_TLB_HI		# Get current PID
 	mfc0	t3, COP_0_TLB_PG_MASK		# Save current pgMask
@@ -333,11 +333,11 @@
 	mtc0	zero, COP_0_STATUS_REG		# Disable interrupts
 	ITLBNOPFIX
 	and	t1, a0, 0x1000			# t1 = Even/Odd flag
-	li	v0, (PG_HVPN | PG_ASID)
+	li	v0, (PTE_HVPN | PTE_ASID)
 	and	a0, a0, v0
 	_MFC0	t0, COP_0_TLB_HI		# Save current PID
 	_MTC0	a0, COP_0_TLB_HI		# Init high reg
-	and	a2, a1, PG_G			# Copy global bit
+	and	a2, a1, PTE_G			# Copy global bit
 	MIPS_CPU_NOP_DELAY
 	tlbp					# Probe for the entry.
 	_SLL	a1, a1, WIRED_SHIFT
@@ -483,7 +483,7 @@
 	tlbr					# obtain an entry
 	MIPS_CPU_NOP_DELAY
 	_MFC0	a0, COP_0_TLB_LO1
-	and	a0, a0, PG_G			# check to see it has G bit
+	and	a0, a0, PTE_G			# check to see it has G bit
 	bnez	a0, 2f
 	nop