From owner-svn-src-head@freebsd.org Tue Nov 17 16:09:27 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D381EA31150; Tue, 17 Nov 2015 16:09:27 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A855F1E9D; Tue, 17 Nov 2015 16:09:27 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tAHG9QLn070083; Tue, 17 Nov 2015 16:09:26 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tAHG9QPh070082; Tue, 17 Nov 2015 16:09:26 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201511171609.tAHG9QPh070082@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Tue, 17 Nov 2015 16:09:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290990 - head/sys/powerpc/aim X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Nov 2015 16:09:28 -0000 Author: nwhitehorn Date: Tue Nov 17 16:09:26 2015 New Revision: 290990 URL: https://svnweb.freebsd.org/changeset/base/290990 Log: Make native page table access endian-safe. Even on CPUs running in little-endian mode, the hardware page table is big-endian. This is a no-op on all currently supported systems. MFC after: 1 month Modified: head/sys/powerpc/aim/moea64_native.c Modified: head/sys/powerpc/aim/moea64_native.c ============================================================================== --- head/sys/powerpc/aim/moea64_native.c Tue Nov 17 16:07:43 2015 (r290989) +++ head/sys/powerpc/aim/moea64_native.c Tue Nov 17 16:09:26 2015 (r290990) @@ -230,7 +230,7 @@ moea64_pte_synch_native(mmu_t mmu, struc moea64_pte_from_pvo(pvo, &properpt); rw_rlock(&moea64_eviction_lock); - if ((pt->pte_hi & LPTE_AVPN_MASK) != + if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != (properpt.pte_hi & LPTE_AVPN_MASK)) { /* Evicted */ rw_runlock(&moea64_eviction_lock); @@ -257,7 +257,7 @@ moea64_pte_clear_native(mmu_t mmu, struc moea64_pte_from_pvo(pvo, &properpt); rw_rlock(&moea64_eviction_lock); - if ((pt->pte_hi & LPTE_AVPN_MASK) != + if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != (properpt.pte_hi & LPTE_AVPN_MASK)) { /* Evicted */ rw_runlock(&moea64_eviction_lock); @@ -268,11 +268,15 @@ moea64_pte_clear_native(mmu_t mmu, struc /* See "Resetting the Reference Bit" in arch manual */ PTESYNC(); /* 2-step here safe: precision is not guaranteed */ - ptelo = pt->pte_lo; + ptelo = be64toh(pt->pte_lo); /* One-byte store to avoid touching the C bit */ ((volatile uint8_t *)(&pt->pte_lo))[6] = +#if BYTE_ORDER == BIG_ENDIAN ((uint8_t *)(&properpt.pte_lo))[6]; +#else + ((uint8_t *)(&properpt.pte_lo))[1]; +#endif rw_runlock(&moea64_eviction_lock); critical_enter(); @@ -297,7 +301,7 @@ moea64_pte_unset_native(mmu_t mmu, struc moea64_pte_from_pvo(pvo, &properpt); rw_rlock(&moea64_eviction_lock); - if ((pt->pte_hi & LPTE_AVPN_MASK) != + if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) != (properpt.pte_hi & LPTE_AVPN_MASK)) { /* Evicted */ moea64_pte_overflow--; @@ -311,7 +315,7 @@ moea64_pte_unset_native(mmu_t mmu, struc */ isync(); critical_enter(); - pt->pte_hi = (pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED; + pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED); PTESYNC(); TLBIE(pvo->pvo_vpn); ptelo = be64toh(pt->pte_lo); @@ -337,13 +341,13 @@ moea64_pte_replace_native(mmu_t mmu, str moea64_pte_from_pvo(pvo, &properpt); rw_rlock(&moea64_eviction_lock); - if ((pt->pte_hi & LPTE_AVPN_MASK) != + if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) != (properpt.pte_hi & LPTE_AVPN_MASK)) { rw_runlock(&moea64_eviction_lock); return (-1); } - pt->pte_hi = properpt.pte_hi; - ptelo = pt->pte_lo; + pt->pte_hi = htobe64(properpt.pte_hi); + ptelo = be64toh(pt->pte_lo); rw_runlock(&moea64_eviction_lock); } else { /* Otherwise, need reinsertion and deletion */ @@ -571,9 +575,9 @@ moea64_insert_to_pteg_native(struct lpte * Update the PTE as per "Adding a Page Table Entry". Lock is released * by setting the high doubleworld. */ - pt->pte_lo = pvo_pt->pte_lo; + pt->pte_lo = htobe64(pvo_pt->pte_lo); EIEIO(); - pt->pte_hi = pvo_pt->pte_hi; + pt->pte_hi = htobe64(pvo_pt->pte_hi); PTESYNC(); /* Keep statistics */