Date: Thu, 16 Jul 2015 08:22:48 +0000 From: "wma_semihalf.com (Wojciech Macek)" <phabric-noreply@FreeBSD.org> To: freebsd-arm@freebsd.org Subject: [Differential] [Updated, 27 lines] D3093: ARM64 TCR register update Message-ID: <c27a3d58d9ec98fe7aeab5af4c0d0102@localhost.localdomain> In-Reply-To: <differential-rev-PHID-DREV-qvctvfcls3krqccl2a3p-req@FreeBSD.org> References: <differential-rev-PHID-DREV-qvctvfcls3krqccl2a3p-req@FreeBSD.org>
next in thread | previous in thread | raw e-mail | index | archive | help
--b1_c27a3d58d9ec98fe7aeab5af4c0d0102 Content-Type: text/plain; charset = "utf-8" Content-Transfer-Encoding: 8bit wma_semihalf.com retitled this revision from "ARMv8 locore.S cleanup and TCR register update" to "ARM64 TCR register update". wma_semihalf.com updated the summary for this revision. wma_semihalf.com updated this revision to Diff 7000. REPOSITORY rS FreeBSD src repository CHANGES SINCE LAST UPDATE https://reviews.freebsd.org/D3093?vs=6962&id=7000 REVISION DETAIL https://reviews.freebsd.org/D3093 AFFECTED FILES sys/arm64/arm64/locore.S sys/arm64/include/armreg.h CHANGE DETAILS diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -200,6 +200,28 @@ #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) +#define TCR_SH1_SHIFT 28 +#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) +#define TCR_ORGN1_SHIFT 26 +#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) +#define TCR_IRGN1_SHIFT 24 +#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) +#define TCR_SH0_SHIFT 12 +#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) +#define TCR_ORGN0_SHIFT 10 +#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) +#define TCR_IRGN0_SHIFT 8 +#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) + +#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ + (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) + +#ifdef SMP +#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) +#else +#define TCR_SMP_ATTRS 0 +#endif + #define TCR_T1SZ_SHIFT 16 #define TCR_T0SZ_SHIFT 0 #define TCR_TxSZ(x) (((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT)) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -27,6 +27,8 @@ */ #include "assym.s" +#include "opt_kstack_pages.h" + #include <sys/syscall.h> #include <machine/asm.h> #include <machine/armreg.h> @@ -535,7 +537,8 @@ /* Device Normal, no cache Normal, write-back */ .quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2) tcr: - .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K) + .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \ + TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ EMAIL PREFERENCES https://reviews.freebsd.org/settings/panel/emailpreferences/ To: wma_semihalf.com, zbb, emaste, andrew Cc: imp, andrew, freebsd-arm-list, emaste --b1_c27a3d58d9ec98fe7aeab5af4c0d0102 Content-Type: text/x-patch; charset=utf-8; name="D3093.7000.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="D3093.7000.patch" ZGlmZiAtLWdpdCBhL3N5cy9hcm02NC9pbmNsdWRlL2FybXJlZy5oIGIvc3lzL2FybTY0L2luY2x1 ZGUvYXJtcmVnLmgKLS0tIGEvc3lzL2FybTY0L2luY2x1ZGUvYXJtcmVnLmgKKysrIGIvc3lzL2Fy bTY0L2luY2x1ZGUvYXJtcmVnLmgKQEAgLTIwMCw2ICsyMDAsMjggQEAKICNkZWZpbmUJVENSX1RH MV80SwkoMiA8PCBUQ1JfVEcxX1NISUZUKQogI2RlZmluZQlUQ1JfVEcxXzY0SwkoMyA8PCBUQ1Jf VEcxX1NISUZUKQogCisjZGVmaW5lCVRDUl9TSDFfU0hJRlQJMjgKKyNkZWZpbmUJVENSX1NIMV9J UwkoMHgzVUwgPDwgVENSX1NIMV9TSElGVCkKKyNkZWZpbmUJVENSX09SR04xX1NISUZUCTI2Cisj ZGVmaW5lCVRDUl9PUkdOMV9XQldBCSgweDFVTCA8PCBUQ1JfT1JHTjFfU0hJRlQpCisjZGVmaW5l CVRDUl9JUkdOMV9TSElGVAkyNAorI2RlZmluZQlUQ1JfSVJHTjFfV0JXQQkoMHgxVUwgPDwgVENS X0lSR04xX1NISUZUKQorI2RlZmluZQlUQ1JfU0gwX1NISUZUCTEyCisjZGVmaW5lCVRDUl9TSDBf SVMJKDB4M1VMIDw8IFRDUl9TSDBfU0hJRlQpCisjZGVmaW5lCVRDUl9PUkdOMF9TSElGVAkxMAor I2RlZmluZQlUQ1JfT1JHTjBfV0JXQQkoMHgxVUwgPDwgVENSX09SR04wX1NISUZUKQorI2RlZmlu ZQlUQ1JfSVJHTjBfU0hJRlQJOAorI2RlZmluZQlUQ1JfSVJHTjBfV0JXQQkoMHgxVUwgPDwgVENS X0lSR04wX1NISUZUKQorCisjZGVmaW5lCVRDUl9DQUNIRV9BVFRSUwkoKFRDUl9JUkdOMF9XQldB IHwgVENSX0lSR04xX1dCV0EpIHxcCisJCQkJKFRDUl9PUkdOMF9XQldBIHwgVENSX09SR04xX1dC V0EpKQorCisjaWZkZWYgU01QCisjZGVmaW5lCVRDUl9TTVBfQVRUUlMJKFRDUl9TSDBfSVMgfCBU Q1JfU0gxX0lTKQorI2Vsc2UKKyNkZWZpbmUJVENSX1NNUF9BVFRSUwkwCisjZW5kaWYKKwogI2Rl ZmluZQlUQ1JfVDFTWl9TSElGVAkxNgogI2RlZmluZQlUQ1JfVDBTWl9TSElGVAkwCiAjZGVmaW5l CVRDUl9UeFNaKHgpCSgoKHgpIDw8IFRDUl9UMVNaX1NISUZUKSB8ICgoeCkgPDwgVENSX1QwU1pf U0hJRlQpKQpkaWZmIC0tZ2l0IGEvc3lzL2FybTY0L2FybTY0L2xvY29yZS5TIGIvc3lzL2FybTY0 L2FybTY0L2xvY29yZS5TCi0tLSBhL3N5cy9hcm02NC9hcm02NC9sb2NvcmUuUworKysgYi9zeXMv YXJtNjQvYXJtNjQvbG9jb3JlLlMKQEAgLTI3LDYgKzI3LDggQEAKICAqLwogCiAjaW5jbHVkZSAi YXNzeW0ucyIKKyNpbmNsdWRlICJvcHRfa3N0YWNrX3BhZ2VzLmgiCisKICNpbmNsdWRlIDxzeXMv c3lzY2FsbC5oPgogI2luY2x1ZGUgPG1hY2hpbmUvYXNtLmg+CiAjaW5jbHVkZSA8bWFjaGluZS9h cm1yZWcuaD4KQEAgLTUzNSw3ICs1MzcsOCBAQAogCQkvKiBEZXZpY2UgICAgICAgICAgICBOb3Jt YWwsIG5vIGNhY2hlICAgICBOb3JtYWwsIHdyaXRlLWJhY2sgKi8KIAkucXVhZAlNQUlSX0FUVFIo MHgwMCwgMCkgfCBNQUlSX0FUVFIoMHg0NCwgMSkgfCBNQUlSX0FUVFIoMHhmZiwgMikKIHRjcjoK LQkucXVhZCAoVENSX1R4U1ooNjQgLSBWSVJUX0JJVFMpIHwgVENSX0FTSURfMTYgfCBUQ1JfVEcx XzRLKQorCS5xdWFkIChUQ1JfVHhTWig2NCAtIFZJUlRfQklUUykgfCBUQ1JfQVNJRF8xNiB8IFRD Ul9URzFfNEsgfCBcCisJICAgIFRDUl9DQUNIRV9BVFRSUyB8IFRDUl9TTVBfQVRUUlMpCiBzY3Rs cl9zZXQ6CiAJLyogQml0cyB0byBzZXQgKi8KIAkucXVhZCAoU0NUTFJfVUNJIHwgU0NUTFJfblRX RSB8IFNDVExSX25UV0kgfCBTQ1RMUl9VQ1QgfCBTQ1RMUl9EWkUgfCBcCgo= --b1_c27a3d58d9ec98fe7aeab5af4c0d0102--
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?c27a3d58d9ec98fe7aeab5af4c0d0102>