From owner-cvs-src-old@FreeBSD.ORG Sat Feb 20 16:30:47 2010 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2F3511065695 for ; Sat, 20 Feb 2010 16:30:47 +0000 (UTC) (envelope-from rrs@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 1BAE78FC08 for ; Sat, 20 Feb 2010 16:30:47 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id o1KGUkLM013739 for ; Sat, 20 Feb 2010 16:30:47 GMT (envelope-from rrs@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id o1KGUkiq013738 for cvs-src-old@freebsd.org; Sat, 20 Feb 2010 16:30:46 GMT (envelope-from rrs@repoman.freebsd.org) Message-Id: <201002201630.o1KGUkiq013738@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to rrs@repoman.freebsd.org using -f From: Randall Stewart Date: Sat, 20 Feb 2010 16:30:29 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/mips/include intr_machdep.h src/sys/mips/rmi interrupt.h intr_machdep.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 20 Feb 2010 16:30:47 -0000 rrs 2010-02-20 16:30:29 UTC FreeBSD src repository Modified files: sys/mips/include intr_machdep.h sys/mips/rmi interrupt.h intr_machdep.c Log: SVN rev 204130 on 2010-02-20 16:30:29Z by rrs Some fixes to the current RMI interrupt handling, changes in this patch are: - (cleanup) remove rmi specific 'struct mips_intrhand' - this is no longer needed since 'struct intr_event' have all the required hooks - add xlr_cpu_establish_hardintr, which has args for pre/post ithread and filter hooks, so that the PCI code can add the PCI controller interrupt ack code here - make 'cpu_establish_hardintr' use the above function. - (fix) change type of eirr/eimr from register_t to uint64_t. These have to be 64bit otherwise we cannot handle interrupts from 32. - (fix) use eimr to mask eirr before checking interrupts, so that we will not handle masked interrupts. Obtained from: C. Jayachandran - c.jayachandran@gmail.com Revision Changes Path 1.4 +0 -14 src/sys/mips/include/intr_machdep.h 1.2 +11 -1 src/sys/mips/rmi/interrupt.h 1.4 +34 -20 src/sys/mips/rmi/intr_machdep.c