Date: Sun, 2 Feb 1997 17:39:15 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: davem@jenolan.rutgers.edu (David S. Miller) Cc: terry@lambert.org, netdev@roxanne.nuclecu.unam.mx, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702030039.RAA09958@phaeton.artisoft.com> In-Reply-To: <199702030029.TAA19968@jenolan.caipgeneral> from "David S. Miller" at Feb 2, 97 07:29:32 pm
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> [ CC: list chopped down, all removed are on the lists remaining ;-) ] > > You are wrong for the BeBox and the SMP PowerMac PPC603 hardware, > which are only MEI (no 'S'). I don't know how Intel-centric you > are, but I'd just as soon see an entry under SMP, seperate from > the CPU architecture, in the build tree. > > I assume even without the shared cache state they do things > reasonably. For example, if 1 asks for a line, and 2 has it but > modified he invalidates and then 1 gets the latest copy from that > invalidation. I also hope they don't invalidate in this case out to > memory, if they do the bus traffic on those boxes must be unpleasant. > This is a bad scheme even if 2 gets his copy stright from the others > cache even though he himself is pushing straight to ram. The PPC 603 SMP implementation is capable of only two processors. It operates by replacing the L2 cache with glue logic to force MEI synchronization of processor L1 cache data. I am not totally sure how this handles writes to the L2. In the Intel case, the protection against invalidation out to memory is implemented by the MMU where the "invalidate to memory" is really "invalidate to L2 cache". It is very likely that it invalidates to memory (IMO), since I have not seen a lot of complex ASIC work being described in the design (otherwise they would have, at least, a shared L2 cache). In any case, I fear Intel-centrism... Regards, Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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