From owner-p4-projects@FreeBSD.ORG Thu Mar 29 14:42:23 2007 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id A1CF716A402; Thu, 29 Mar 2007 14:42:23 +0000 (UTC) X-Original-To: perforce@FreeBSD.org Delivered-To: perforce@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 79A6716A400 for ; Thu, 29 Mar 2007 14:42:23 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [69.147.83.41]) by mx1.freebsd.org (Postfix) with ESMTP id 6A67C13C44C for ; Thu, 29 Mar 2007 14:42:23 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.8/8.13.8) with ESMTP id l2TEgNhE039623 for ; Thu, 29 Mar 2007 14:42:23 GMT (envelope-from gonzo@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.8/8.13.8/Submit) id l2TEgNVs039617 for perforce@freebsd.org; Thu, 29 Mar 2007 14:42:23 GMT (envelope-from gonzo@FreeBSD.org) Date: Thu, 29 Mar 2007 14:42:23 GMT Message-Id: <200703291442.l2TEgNVs039617@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to gonzo@FreeBSD.org using -f From: Oleksandr Tymoshenko To: Perforce Change Reviews Cc: Subject: PERFORCE change 116834 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Mar 2007 14:42:24 -0000 http://perforce.freebsd.org/chv.cgi?CH=116834 Change 116834 by gonzo@gonzo_jeeves on 2007/03/29 14:41:43 o Fill new cpuinfo fields with values based on config0 and config1. Affected files ... .. //depot/projects/mips2/src/sys/mips/mips/cpu.c#17 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/mips/cpu.c#17 (text+ko) ==== @@ -138,6 +138,7 @@ cfg0 = mips_rd_config(); cpuinfo->tlb_type = ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT); + cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; /* If config register selection 1 does not exist, exit. */ if (!(cfg0 & MIPS3_CONFIG_CM)) @@ -153,6 +154,8 @@ cpuinfo->l1.ic_linesize = tmp; cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); + cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets + * cpuinfo->l1.ic_nways; } /* L1 data cache. */ @@ -161,6 +164,8 @@ cpuinfo->l1.dc_linesize = tmp; cpuinfo->l1.dc_nways = (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; cpuinfo->l1.dc_nsets = 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); + cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize * cpuinfo->l1.dc_nsets + * cpuinfo->l1.dc_nways; } } @@ -171,7 +176,7 @@ mips_get_identity(&cpuinfo); mips_num_tlb_entries = cpuinfo.tlb_nentries; - mips_config_cache(); + mips_config_cache(&cpuinfo); mips_vector_init(); mips_icache_sync_all();