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Date:      Sun, 4 Nov 2001 15:28:35 -0800
From:      Marcel Moolenaar <marcel@xcllnt.net>
To:        Doug Rabson <dfr@nlsystems.com>
Cc:        ia64@FreeBSD.org
Subject:   Additional DTR mappings?
Message-ID:  <20011104152835.A2305@dhcp01.pn.xcllnt.net>
In-Reply-To: <20011102093142.T549-100000@salmon.nlsystems.com>
References:  <20011101193936.A575@dhcp01.pn.xcllnt.net> <20011102093142.T549-100000@salmon.nlsystems.com>

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On Fri, Nov 02, 2001 at 09:35:26AM +0000, Doug Rabson wrote:
> 
> Well I'm up and running now with the jumpers set according to this
> document. Both processors pass their self test etc. and the kernel boots.
> We will have to see if any other differences appear when we get the second
> processor to actually do some real work...

Ok. I have coded the AP rendezvous code and I simply cannot make
it give any sign of life. I'm now thinking that the IPI does
not reach the processor, even though the test IPI sent from the
BSP is received by the BSP.

Two questions:

1. I'm trying to insert a DTR of type PTE_MA_UC that covers the
   processor interrupt block, but that's causing an exception:

fatal kernel trap:                                                              
                                                                                
    trap vector = 0x18 (General Exception)                                      
    cr.iip      = 0xe000000000880a70                                            
    cr.ipsr     = 0x101008022010 (mfl,ic,dt,rt,cpl=0,it,ri=0,bn)                
    cr.isr      = 0x8000000030 (ni,ei=0)                                        
    cr.ifa      = 0xc0000000fee00000                                            
    cr.iim      = 0xf4                                                          
    curthread   = 0xe000000000a5f8e0                                            
        pid = 0, comm =                                                         
                                                                                
Stopped at      sapic_read+0x10:        [MMI] st4.rel [r14]=r33;;               

   Does any of you know whether we need to have a mapping for the
   PIB at all? (ie am I on the right track)?

2. We also don't have a mapping for the frame buffer (type PTE_MA_UC).
   It looks to me that we need that as well. Is this right?

-- 
 Marcel Moolenaar	  USPA: A-39004		 marcel@xcllnt.net

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