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Date:      Tue, 24 Nov 2015 09:13:21 +0000 (UTC)
From:      Konstantin Belousov <kib@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r291242 - head/sys/powerpc/include
Message-ID:  <201511240913.tAO9DLUC032185@repo.freebsd.org>

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Author: kib
Date: Tue Nov 24 09:13:21 2015
New Revision: 291242
URL: https://svnweb.freebsd.org/changeset/base/291242

Log:
  On PowerPC 64bit, the linux-compat mb() definition is implemented with
  lwsync instruction, which does not provide Store/Load barrier.  Fix
  this by using "full" sync barrier for mb().
  
  atomic_store_rel() does not need full barrier, change mb() call there
  to the lwsync instruction if not hitting the known CPU erratas
  (i.e. on 32bit).  Provide powerpc_lwsync() helper to isolate the
  lwsync/sync compile time selection, and use it in atomic_store_rel()
  and several other places which duplicate the code.
  
  Noted by:	alc
  Reviewed and tested by:	nwhitehorn
  Sponsored by:	The FreeBSD Foundation

Modified:
  head/sys/powerpc/include/atomic.h

Modified: head/sys/powerpc/include/atomic.h
==============================================================================
--- head/sys/powerpc/include/atomic.h	Tue Nov 24 09:08:31 2015	(r291241)
+++ head/sys/powerpc/include/atomic.h	Tue Nov 24 09:13:21 2015	(r291242)
@@ -48,7 +48,7 @@
  */
 
 #ifdef __powerpc64__
-#define mb()		__asm __volatile("lwsync" : : : "memory")
+#define mb()		__asm __volatile("sync" : : : "memory")
 #define rmb()		__asm __volatile("lwsync" : : : "memory")
 #define wmb()		__asm __volatile("lwsync" : : : "memory")
 #define __ATOMIC_REL()	__asm __volatile("lwsync" : : : "memory")
@@ -61,6 +61,17 @@
 #define __ATOMIC_ACQ()	__asm __volatile("isync" : : : "memory")
 #endif
 
+static __inline void
+powerpc_lwsync(void)
+{
+
+#ifdef __powerpc64__
+	__asm __volatile("lwsync" : : : "memory");
+#else
+	__asm __volatile("sync" : : : "memory");
+#endif
+}
+
 /*
  * atomic_add(p, v)
  * { *p += v; }
@@ -506,7 +517,8 @@ atomic_load_acq_##TYPE(volatile u_##TYPE
 static __inline void						\
 atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)	\
 {								\
-	mb();							\
+								\
+	powerpc_lwsync();					\
 	*p = v;							\
 }
 
@@ -734,34 +746,21 @@ static __inline void
 atomic_thread_fence_acq(void)
 {
 
-	/* See above comment about lwsync being broken on Book-E. */
-#ifdef __powerpc64__
-	__asm __volatile("lwsync" : : : "memory");
-#else
-	__asm __volatile("sync" : : : "memory");
-#endif
+	powerpc_lwsync();
 }
 
 static __inline void
 atomic_thread_fence_rel(void)
 {
 
-#ifdef __powerpc64__
-	__asm __volatile("lwsync" : : : "memory");
-#else
-	__asm __volatile("sync" : : : "memory");
-#endif
+	powerpc_lwsync();
 }
 
 static __inline void
 atomic_thread_fence_acq_rel(void)
 {
 
-#ifdef __powerpc64__
-	__asm __volatile("lwsync" : : : "memory");
-#else
-	__asm __volatile("sync" : : : "memory");
-#endif
+	powerpc_lwsync();
 }
 
 static __inline void



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