From owner-cvs-all@FreeBSD.ORG Tue Oct 25 04:53:29 2005 Return-Path: X-Original-To: cvs-all@FreeBSD.org Delivered-To: cvs-all@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E590716A41F; Tue, 25 Oct 2005 04:53:29 +0000 (GMT) (envelope-from wpaul@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id B816D43D49; Tue, 25 Oct 2005 04:53:29 +0000 (GMT) (envelope-from wpaul@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.1/8.13.1) with ESMTP id j9P4rTOL085861; Tue, 25 Oct 2005 04:53:29 GMT (envelope-from wpaul@repoman.freebsd.org) Received: (from wpaul@localhost) by repoman.freebsd.org (8.13.1/8.13.1/Submit) id j9P4rTJk085860; Tue, 25 Oct 2005 04:53:29 GMT (envelope-from wpaul) Message-Id: <200510250453.j9P4rTJk085860@repoman.freebsd.org> From: Bill Paul Date: Tue, 25 Oct 2005 04:53:29 +0000 (UTC) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Cc: Subject: cvs commit: src/sys/i386/pci pci_cfgreg.c src/sys/amd64/pci pci_cfgreg.c X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Oct 2005 04:53:30 -0000 wpaul 2005-10-25 04:53:29 UTC FreeBSD src repository Modified files: sys/i386/pci pci_cfgreg.c sys/amd64/pci pci_cfgreg.c Log: Modify the pci_cfgdisable() routine to bring it more in line with other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0 to the config address register when using config mechanism 1 to turn off config access. In fact, it can be downright troublesome, since it seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause it to sporadically botch reads from some devices. This is the cause of the missing USP ports problem I was experiencing with my Sun Opteron system. Also correct the case for mechanism 2: it's only necessary to write a 0 to the ENABLE port. Revision Changes Path 1.109 +6 -2 src/sys/amd64/pci/pci_cfgreg.c 1.117 +7 -3 src/sys/i386/pci/pci_cfgreg.c