From owner-freebsd-mips@FreeBSD.ORG Wed Feb 19 18:02:00 2014 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1FCCFAAB; Wed, 19 Feb 2014 18:02:00 +0000 (UTC) Received: from cyrus.watson.org (cyrus.watson.org [198.74.231.69]) by mx1.freebsd.org (Postfix) with ESMTP id EC6341297; Wed, 19 Feb 2014 18:01:59 +0000 (UTC) Received: from fledge.watson.org (fledge.watson.org [198.74.231.63]) by cyrus.watson.org (Postfix) with ESMTPS id 8919D46B62; Wed, 19 Feb 2014 13:01:59 -0500 (EST) Date: Wed, 19 Feb 2014 18:01:59 +0000 (GMT) From: Robert Watson X-X-Sender: robert@fledge.watson.org To: Warner Losh Subject: Re: [RFC] Enable use of UserLocal Register (ULRI) if detected (patches) In-Reply-To: <092B0786-EA73-44D0-81FC-DFB56B14D4D7@bsdimp.com> Message-ID: References: <092B0786-EA73-44D0-81FC-DFB56B14D4D7@bsdimp.com> User-Agent: Alpine 2.00 (BSF 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: "freebsd-mips@freebsd.org" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Feb 2014 18:02:00 -0000 On Wed, 19 Feb 2014, Warner Losh wrote: >> For more information about the ULRI see "MIPS Architecture for Programmers >> Volume III" section 9.9 UserLocal Register (CP0 Register 4, Select 2). > > Thanks for doing this! I would note, BTW, that the current use of TLS in malloc()/free() and today's MIPS exception handler for TLS implementation do introduce a very measurable overhead. I'm left wondering if there is something we can do for unthreaded processes to avoid taking kernel traps on every memory allocation and free for MIPSes without ULRI. (Note that that problem is present before Stacey's patch: the reason we added ULRI support is that our hardware does support ULRI, and we can therefore avoid that nasty overhead ...) I understand there's work on a new MIPS ABI that specifies a TLS register not requiring a trap to read on non-ULRI hardware, but I'm not sure how far that is from being available. Certainly it will require compiler/OS/etc work before it becomes useful to us. Robert