From owner-svn-src-head@freebsd.org Tue Aug 30 02:09:41 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8B4C2BC8AC7; Tue, 30 Aug 2016 02:09:41 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 41A4CC9A; Tue, 30 Aug 2016 02:09:41 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u7U29evt026078; Tue, 30 Aug 2016 02:09:40 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u7U29eoA026077; Tue, 30 Aug 2016 02:09:40 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201608300209.u7U29eoA026077@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Tue, 30 Aug 2016 02:09:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305043 - head/sys/powerpc/mpc85xx X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Aug 2016 02:09:41 -0000 Author: jhibbits Date: Tue Aug 30 02:09:40 2016 New Revision: 305043 URL: https://svnweb.freebsd.org/changeset/base/305043 Log: Attach and LAW problems to fix Summary: 1) Attach problem - mpc85xx_probe() relies on fact that 0xfff0 mask matches all QorIQ CPUs what is not true since e6500. This shall be reworked to match against all supported CPUs. 2) There is no any reason for operating system to re-program or anyhow else touch the LAWs programmed by firmware (u-boot). Right now mpc85xx_attach() removes all LaW entries except for DRAM. This causes MCE to be generated when later any of driver maps DTB-provided hardware addresses which do not exist anymore because corresponding LaWs were removed. Submitted by: Ivan Krivonos Differential Revision: https://reviews.freebsd.org/D7663 Modified: head/sys/powerpc/mpc85xx/platform_mpc85xx.c Modified: head/sys/powerpc/mpc85xx/platform_mpc85xx.c ============================================================================== --- head/sys/powerpc/mpc85xx/platform_mpc85xx.c Tue Aug 30 02:07:15 2016 (r305042) +++ head/sys/powerpc/mpc85xx/platform_mpc85xx.c Tue Aug 30 02:09:40 2016 (r305043) @@ -120,11 +120,16 @@ PLATFORM_DEF(mpc85xx_platform); static int mpc85xx_probe(platform_t plat) { - u_int pvr = mfpvr() >> 16; - - if ((pvr & 0xfff0) == FSL_E500v1) - return (BUS_PROBE_DEFAULT); + u_int pvr = (mfpvr() >> 16) & 0xFFFF; + switch (pvr) { + case FSL_E500v1: + case FSL_E500v2: + case FSL_E500mc: + case FSL_E5500: + case FSL_E6500: + return (BUS_PROBE_DEFAULT); + } return (ENXIO); } @@ -135,9 +140,8 @@ mpc85xx_attach(platform_t plat) const char *soc_name_guesses[] = {"/soc", "soc", NULL}; const char **name; pcell_t ranges[6], acells, pacells, scells; - uint32_t sr; uint64_t ccsrbar, ccsrsize; - int i, law_max, tgt; + int i; if ((cpus = OF_finddevice("/cpus")) != -1) { for (maxcpu = 0, child = OF_child(cpus); child != 0; @@ -194,23 +198,6 @@ mpc85xx_attach(platform_t plat) mpc85xx_fix_errata(ccsrbar_va); mpc85xx_enable_l3_cache(); - /* - * Clear local access windows. Skip DRAM entries, so we don't shoot - * ourselves in the foot. - */ - law_max = law_getmax(); - for (i = 0; i < law_max; i++) { - sr = ccsr_read4(OCP85XX_LAWSR(i)); - if ((sr & OCP85XX_ENA_MASK) == 0) - continue; - tgt = (sr & 0x01f00000) >> 20; - if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || - tgt == OCP85XX_TGTIF_RAM_INTL) - continue; - - ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK); - } - return (0); }