Date: Tue, 13 Sep 2016 14:10:49 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r305767 - head/sys/arm64/arm64 Message-ID: <201609131410.u8DEAnAD092017@repo.freebsd.org>
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Author: andrew Date: Tue Sep 13 14:10:49 2016 New Revision: 305767 URL: https://svnweb.freebsd.org/changeset/base/305767 Log: Add a warning about a known erratum we have observed on ThunderX pass 1.1. As this is evaluation hardware with only a few users, and there is a lack of information add a warning when booting on this hardware. Reported by: cognet Obtained from: ABT Systems Ltd MFC after: Instant Sponsored by: The FreeBSD Foundation Modified: head/sys/arm64/arm64/identcpu.c Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Tue Sep 13 13:23:24 2016 (r305766) +++ head/sys/arm64/arm64/identcpu.c Tue Sep 13 14:10:49 2016 (r305767) @@ -179,6 +179,28 @@ print_cpu_features(u_int cpu) } printf("\n"); + /* + * There is a hardware errata where, if one CPU is performing a TLB + * invalidation while another is performing a store-exclusive the + * store-exclusive may return the wrong status. A workaround seems + * to be to use an IPI to invalidate on each CPU, however given the + * limited number of affected units (pass 1.1 is the evaluation + * hardware revision), and the lack of information from Cavium + * this has not been implemented. + * + * At the time of writing this the only information is from: + * https://lkml.org/lkml/2016/8/4/722 + */ + /* + * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on it's own also + * triggers on pass 2.0+. + */ + if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && + CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) + printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " + "hardware bugs that may cause the incorrect operation of " + "atomic operations.\n"); + if (cpu != 0 && cpu_print_regs == 0) return;
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