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Date: Mon, 24 Feb 1997 10:19:16 -0800 (PST)
From: Chris Timmons <skynyrd@opus.cts.cwu.edu>
To: Bruce Evans <bde@zeta.org.au>
cc: nate@mt.sri.com, hardware@freebsd.org
Subject: Re: Memory speed (was Re: _big_ IDE disks?)
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Hmmm....

On the p/i p6np5 pro200 machine (award bios) permits x-2-2-3 as the most
aggressive timing for both read/write (which were set.)

There is also "RAS Precharge" and "RAS to CAS" delay which are unexplained
in the manual.  Their values "3T" each by default seem to be a divisor, as
when I lowered the delay to 2T, I immediately started getting the kinds of
results in the benchmark that the other fellow was talking about on his
ppro - ~65MB.

The RAS Precharge could go to 4T, which I set, and realized a slight
performance gain in the benchmark to ~85MB, up from ~80MB.  I'll be
interested to see how this affects stability and if there is a measurable
gain on the make world times (-current building yet? :)

Thanks for the info about this... I'll fiddle with the t2p4 boards later
on.

-Chris



On Tue, 25 Feb 1997, Bruce Evans wrote:

> I use the standard knobs with everything turned up high.  An x-2-2-2
> write burst cycle is most important for this benchmark.
> 
> Bruce
> 
> Script started on Tue Feb 25 03:04:55 1997
> ttyv1:bde@alphplex:/tmp> dd if=/dev/zero of=/dev/null bs=1m count=1000
> 1000+0 records in
> 1000+0 records out
> 1048576000 bytes transferred in 8.389282 secs (124989958 bytes/sec)
> ttyv1:bde@alphplex:/tmp> exit
> 
> Script done on Tue Feb 25 03:05:07 1997
> 
> Calibrating clock(s) relative to mc146818A clock ... i586 clock: 132622829 Hz, i8254 clock: 1193105 Hz
> CPU: Pentium (132.62-MHz 586-class CPU)
>   Origin = "GenuineIntel"  Id = 0x52b  Stepping=11
>   Features=0x1bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8>
> real memory  = 33554432 (32768K bytes)
> avail memory = 30412800 (29700K bytes)
> DEVFS: ready for devices
> Probing for devices on PCI bus 0:
> chip0 <Intel 82437FX PCI cache memory controller> rev 2 on pci0:0:0
>