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Date:      Thu, 23 Aug 2012 15:50:35 -0600
From:      Warner Losh <imp@bsdimp.com>
To:        Ian Lepore <freebsd@damnhippie.dyndns.org>
Cc:        freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org
Subject:   Re: Partial cacheline flush problems on ARM and MIPS
Message-ID:  <3A08EB08-2BBF-4B0F-97F2-A3264754C4B7@bsdimp.com>
In-Reply-To: <1345757300.27688.535.camel@revolution.hippie.lan>
References:  <1345757300.27688.535.camel@revolution.hippie.lan>

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On Aug 23, 2012, at 3:28 PM, Ian Lepore wrote:
> A recent innocuous change to the USB driver code caused intermittant
> errors in the umass(4) driver on ARM and MIPS platforms, and this

I think the proper solution is to segregate DMA and non-DMA parts of =
structures so that you don't have both sharing a cache line.

I also wonder why we don't allocate the DMA memory for these structures =
separately from the non-DMA parts.  This would eliminate the =
USB_CACHE_BYTES kludge (which is CPU dependent, not arch dependent) and =
move the knowledge of this junk into busdma layer where it belongs.  =
=46rom my understanding of the issue, this would completely eliminate =
the problem forever!

Sharing a cacheline between something that is DMA aware and something =
that is just begging for trouble.  We're  doing more work than we need =
to to support this dubious feature and we'd be miles ahead if we could =
not share at all.

Warner




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