Date: Mon, 05 Jan 2015 15:48:24 -0500 From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r276724 - in head/sys: amd64/amd64 dev/acpica i386/i386 kern sys x86/x86 Message-ID: <54AAF898.2000705@FreeBSD.org> In-Reply-To: <201501052044.t05KijiD033353@svn.freebsd.org> References: <201501052044.t05KijiD033353@svn.freebsd.org>
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On 1/5/15 3:44 PM, John Baldwin wrote: > Author: jhb > Date: Mon Jan 5 20:44:44 2015 > New Revision: 276724 > URL: https://svnweb.freebsd.org/changeset/base/276724 > > Log: > On some Intel CPUs with a P-state but not C-state invariant TSC the TSC > may also halt in C2 and not just C3 (it seems that in some cases the BIOS > advertises its C3 state as a C2 state in _CST). Just play it safe and > disable both C2 and C3 states if a user forces the use of the TSC as the > timecounter on such CPUs. > > PR: 192316 > Differential Revision: https://reviews.freebsd.org/D1441 > No objection from: jkim > MFC after: 1 week Oops, forgot to credit the submitter who tested the patch (a few iterations in fact): Tested by: Jan Kokemüller <jan.kokemueller@gmail.com> -- John Baldwin
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