Date: Sun, 30 Nov 1997 06:15:59 +1100 From: Bruce Evans <bde@zeta.org.au> To: bde@zeta.org.au, jak@cetlink.net Cc: hackers@freebsd.org Subject: Re: 650 UART, SIO driver, 8259 PIC Message-ID: <199711291915.GAA14582@godzilla.zeta.org.au>
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>>According to the diagram in the Intel data sheet, and my experiments, >>the edge latch isn't cleared until the external interrupt goes away. >> >>> 10 B3 of the IRR is set to 0 (IRR is unfrozen and B3 of >>> ESR is zero). > >I don't know what experiment you performed, but using a volt meter and >... I set an IRQ input to known states (driving it with a 16x50), disabled CPU interrupts, and read the IRR. The behaviour depends on whether the the interrupt has been latched when interrupts are disabled. >>>other useful work, by clearing the INT output of the last UART before >>>any of the previously drained UARTs can raise their INT output again, >>>you will have at least one down/up transition on the IRQ line. If you >> >>That would be a pessimization. It requires _two_ extra outputs per >>port (one to mess up the INT enable and one to restore it). > >That's not what I meant. :-( I'm not going to poke the UART twice to >toggle interrupt enable. > >The act of draining the FIFO will cause each UART to pull its INT >output (pin 30 on a 40-pin DIP) to ground. In the case of an 8-port Not if there is a transmitter, modem status or line status interrupt pending at the instant the FIFO is drained (to just below the trigger level). >shared interrupt card, at the instant the last UART is drained below >its FIFO trigger level, all eight INT output pins will be at ground. Not if you didn't drain one of the previous UARTs (because its fifo wasn't full when you looked at it; draining partially full fifos would be a pessimization). Then there may be a receiver interrupt pending on one of the previous UARTs. Similarly, not if a transmitter, modem status or line status interrupt has become pending on one of the previous UARTs. Bruce
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