From owner-svn-src-all@freebsd.org Tue Sep 13 14:14:41 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0CE24BD9EB7; Tue, 13 Sep 2016 14:14:41 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CEFF5FE9; Tue, 13 Sep 2016 14:14:40 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u8DEEe6g095483; Tue, 13 Sep 2016 14:14:40 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u8DEEeZc095482; Tue, 13 Sep 2016 14:14:40 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201609131414.u8DEEeZc095482@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 13 Sep 2016 14:14:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r305768 - stable/11/sys/arm64/arm64 X-SVN-Group: stable-11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Sep 2016 14:14:41 -0000 Author: andrew Date: Tue Sep 13 14:14:39 2016 New Revision: 305768 URL: https://svnweb.freebsd.org/changeset/base/305768 Log: MFC 305767: Add a warning about a known erratum we have observed on ThunderX pass 1.1. As this is evaluation hardware with only a few users, and there is a lack of information add a warning when booting on this hardware. Modified: stable/11/sys/arm64/arm64/identcpu.c Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/arm64/arm64/identcpu.c ============================================================================== --- stable/11/sys/arm64/arm64/identcpu.c Tue Sep 13 14:10:49 2016 (r305767) +++ stable/11/sys/arm64/arm64/identcpu.c Tue Sep 13 14:14:39 2016 (r305768) @@ -179,6 +179,28 @@ print_cpu_features(u_int cpu) } printf("\n"); + /* + * There is a hardware errata where, if one CPU is performing a TLB + * invalidation while another is performing a store-exclusive the + * store-exclusive may return the wrong status. A workaround seems + * to be to use an IPI to invalidate on each CPU, however given the + * limited number of affected units (pass 1.1 is the evaluation + * hardware revision), and the lack of information from Cavium + * this has not been implemented. + * + * At the time of writing this the only information is from: + * https://lkml.org/lkml/2016/8/4/722 + */ + /* + * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on it's own also + * triggers on pass 2.0+. + */ + if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 && + CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) + printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known " + "hardware bugs that may cause the incorrect operation of " + "atomic operations.\n"); + if (cpu != 0 && cpu_print_regs == 0) return;