From nobody Mon Sep 2 15:02:26 2024 X-Original-To: dev-commits-ports-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4WyBnG5yTdz5TYKQ; Mon, 02 Sep 2024 15:02:26 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4WyBnG5Y18z4lQr; Mon, 2 Sep 2024 15:02:26 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1725289346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=mshQhHrE6I6t3kxSpm4UI3bVjlYYMcXHqA1aRcadJRw=; b=nJErWpJmdjk5V1tXCim/I+ebi990LYY0LZSC2moKzpjjRGd2jflATOj5tNWS8sYGHFxUDk Qvwfo2vURuPmolQCWPP/o6kg+A1vlMHt2UBCcAi0ONdPHUuBvxzP4kodAIIkVxcm2eh+97 e5+lQBdBl/X0Fy+2shYKmp8Ix570C5Aw1ZlyxFRMQlhYLXrf9SDQtguf135b651bY1fl6e jKKsLgpFr3O7LPPTQ5YkF2R/1nkPk24WceT0bgvhujYgPbn2YRUwLCikwSyZDw5qtH36fb ELVGX8KQslGmnQSDPSui3XVbZFijcyZ5Kl0BMByAodpFoMhMQhz6tXbmoKR6ZA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1725289346; a=rsa-sha256; cv=none; b=Si1jtJN+QKpTyJ1FbcZltZxBNpH0ezqMA7sY87hQXcttIjW3EntoIySIBr+OylJyEcQ8vg meA5lNBbh3ht7wZYDFUdfeg1/khbUtRQ2mLqMlp0wf58fS7p9o6dMKGqcV8SBuUfZIXgoe +V0d1AfjkzLNFOmsVc0LLY3pFXaHLc0K3rOfW63qUEwTi5mVC+u74ZOEQ2cEFPuGIpW6cx k4+n/jCefY3wYzSlcioCtgJqKgCv9aTN3QLSNM0rC+3uVM/h/NrWEg1uvj1MOgYxnaFltD 2yyOUa6IGUKEOveMgQBRQPw1QBJTq2WoXFK6zH4iDoZOUX8iNjkrlcGm14QBUw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1725289346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=mshQhHrE6I6t3kxSpm4UI3bVjlYYMcXHqA1aRcadJRw=; b=R1DN83JBQTwZDZNwduRhlDkISD26d23KOn3bwARfFHIQLu7my7mchzMsMmgTKyez2n0Wq8 rodkDDPKHhN5PkqGdJM9r/5YWJ8Fb0gLHt503njSOeLkVBQqG0o0xL8UNry59Pczj6OEEJ rYiUklxvhSXRyiFsUR05H70TC1XF758u0FPhpPMHwfxV2Kl3Uoodei9nY1kl06lLbs0SqV ZFL2UoHmkac0HfUlhouof3cspqGuhIz8E4A6xT3Tqh7eQLA/eUzlTDgTR2kgMp2wqEmN7U JZGK1n52ZGM/UQ1YvKe6hbS2pdvLH1kCQNbTiNzP7yHfYDDM4yFLoUcju4Jwnw== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4WyBnG59Dnz1Gkt; Mon, 2 Sep 2024 15:02:26 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 482F2Qju044350; Mon, 2 Sep 2024 15:02:26 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 482F2QVF044347; Mon, 2 Sep 2024 15:02:26 GMT (envelope-from git) Date: Mon, 2 Sep 2024 15:02:26 GMT Message-Id: <202409021502.482F2QVF044347@gitrepo.freebsd.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org From: Ruslan Bukin Subject: git: 5838f13ec07f - main - sysutils/u-boot-bhyve-riscv: New port List-Id: Commits to the main branch of the FreeBSD ports repository List-Archive: https://lists.freebsd.org/archives/dev-commits-ports-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-ports-main@freebsd.org Sender: owner-dev-commits-ports-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: br X-Git-Repository: ports X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 5838f13ec07f5b04e85a17ab28234eba8b1f7229 Auto-Submitted: auto-generated The branch main has been updated by br: URL: https://cgit.FreeBSD.org/ports/commit/?id=5838f13ec07f5b04e85a17ab28234eba8b1f7229 commit 5838f13ec07f5b04e85a17ab28234eba8b1f7229 Author: Ruslan Bukin AuthorDate: 2024-09-02 14:47:12 +0000 Commit: Ruslan Bukin CommitDate: 2024-09-02 15:01:50 +0000 sysutils/u-boot-bhyve-riscv: New port Configuration of u-boot for bhyve hypervisor (RISC-V architecture). This intended to run in RISC-V supervisor ("S") mode as a guest OS. Reviewed By: arrowd, manu Differential Revision: https://reviews.freebsd.org/D46257 --- sysutils/Makefile | 1 + sysutils/u-boot-bhyve-riscv/Makefile | 12 +++ .../files/patch-arch_riscv_Kconfig | 21 +++++ .../files/patch-arch_riscv_dts_Makefile | 10 +++ .../files/patch-arch_riscv_dts_bhyve-riscv.dts | 14 ++++ .../patch-board_emulation_bhyve-riscv_Kconfig | 94 ++++++++++++++++++++++ .../patch-board_emulation_bhyve-riscv_MAINTAINERS | 9 +++ .../patch-board_emulation_bhyve-riscv_Makefile | 6 ++ ...patch-board_emulation_bhyve-riscv_bhyve-riscv.c | 75 +++++++++++++++++ .../patch-configs_bhyve-riscv64_smode_defconfig | 44 ++++++++++ .../files/patch-include_configs_bhyve-riscv.h | 29 +++++++ sysutils/u-boot-bhyve-riscv/pkg-descr | 9 +++ 12 files changed, 324 insertions(+) diff --git a/sysutils/Makefile b/sysutils/Makefile index 8e4c03d8eb8c..08d06d7d6c0a 100644 --- a/sysutils/Makefile +++ b/sysutils/Makefile @@ -1510,6 +1510,7 @@ SUBDIR += u-boot-bananapim2 SUBDIR += u-boot-beaglebone SUBDIR += u-boot-bhyve-arm64 + SUBDIR += u-boot-bhyve-riscv SUBDIR += u-boot-chip SUBDIR += u-boot-clearfog SUBDIR += u-boot-cubieboard diff --git a/sysutils/u-boot-bhyve-riscv/Makefile b/sysutils/u-boot-bhyve-riscv/Makefile new file mode 100644 index 000000000000..bfdc0e5ce8df --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/Makefile @@ -0,0 +1,12 @@ +MASTERDIR= ${.CURDIR}/../u-boot-master + +MODEL= bhyve-riscv +BOARD_CONFIG= bhyve-riscv64_smode_defconfig +FAMILY= bhyve +UBOOT_ARCH= riscv64 + +UBOOT_PLIST= u-boot.bin + +EXTRA_PATCHES= ${.CURDIR}/files/ + +.include "${MASTERDIR}/Makefile" diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_Kconfig b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_Kconfig new file mode 100644 index 000000000000..e03aa4903bb8 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_Kconfig @@ -0,0 +1,21 @@ +--- arch/riscv/Kconfig.orig ++++ arch/riscv/Kconfig +@@ -24,6 +24,10 @@ config TARGET_QEMU_VIRT + bool "Support QEMU Virt Board" + select BOARD_LATE_INIT + ++config TARGET_BHYVE ++ bool "FreeBSD bhyve" ++ select DM ++ + config TARGET_SIFIVE_UNLEASHED + bool "Support SiFive Unleashed Board" + +@@ -82,6 +86,7 @@ config SPL_ZERO_MEM_BEFORE_USE + # board-specific options below + source "board/andestech/ae350/Kconfig" + source "board/emulation/qemu-riscv/Kconfig" ++source "board/emulation/bhyve-riscv/Kconfig" + source "board/microchip/mpfs_icicle/Kconfig" + source "board/openpiton/riscv64/Kconfig" + source "board/sifive/unleashed/Kconfig" diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_Makefile b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_Makefile new file mode 100644 index 000000000000..af98c42857d7 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_Makefile @@ -0,0 +1,10 @@ +--- arch/riscv/dts/Makefile.orig ++++ arch/riscv/dts/Makefile +@@ -11,6 +11,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb + dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb + dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb + dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb ++dtb-$(CONFIG_TARGET_BHYVE) += bhyve-riscv.dtb + + include $(srctree)/scripts/Makefile.dts + diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_bhyve-riscv.dts b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_bhyve-riscv.dts new file mode 100644 index 000000000000..4e6279284148 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-arch_riscv_dts_bhyve-riscv.dts @@ -0,0 +1,14 @@ +--- arch/riscv/dts/bhyve-riscv.dts ++++ arch/riscv/dts/bhyve-riscv.dts +@@ -0,0 +1,11 @@ ++// SPDX-License-Identifier: GPL-2.0+ OR MIT ++/* ++ * Empty device tree for bhyve_riscv ++ ++ * Copyright 2021 Google LLC ++ */ ++ ++/dts-v1/; ++ ++/ { ++}; diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Kconfig b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Kconfig new file mode 100644 index 000000000000..56003d245dda --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Kconfig @@ -0,0 +1,94 @@ +--- board/emulation/bhyve-riscv/Kconfig.orig ++++ board/emulation/bhyve-riscv/Kconfig +@@ -0,0 +1,91 @@ ++if TARGET_BHYVE ++ ++config SYS_BOARD ++ default "bhyve-riscv" ++ ++config SYS_VENDOR ++ default "emulation" ++ ++config SYS_CPU ++ default "generic" ++ ++config SYS_CONFIG_NAME ++ default "bhyve-riscv" ++ ++config TEXT_BASE ++ default 0x81200000 if SPL ++ default 0x80000000 if !RISCV_SMODE ++ default 0x100000000 if RISCV_SMODE && ARCH_RV64I ++ default 0x80400000 if RISCV_SMODE && ARCH_RV32I ++ ++config SPL_TEXT_BASE ++ default 0x80000000 ++ ++config SPL_OPENSBI_LOAD_ADDR ++ hex ++ default 0x80100000 ++ ++config PRE_CON_BUF_ADDR ++ hex ++ default 0x81000000 ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ select GENERIC_RISCV ++ select SUPPORT_SPL ++ select QFW if ACPI ++ select QFW_MMIO if QFW ++ imply AHCI ++ imply SMP ++ imply BOARD_LATE_INIT ++ imply PCI_INIT_R ++ imply SPL_RAM_SUPPORT ++ imply SPL_RAM_DEVICE ++ imply CMD_PCI ++ imply CMD_POWEROFF ++ imply CMD_SBI ++ imply CMD_SCSI ++ imply CMD_PING ++ imply CMD_EXT2 ++ imply CMD_EXT4 ++ imply CMD_FAT ++ imply CMD_FS_GENERIC ++ imply DOS_PARTITION ++ imply ISO_PARTITION ++ imply EFI_PARTITION ++ imply SCSI_AHCI ++ imply AHCI_PCI ++ imply E1000 ++ imply PCI ++ imply NVME_PCI ++ imply PCIE_ECAM_GENERIC ++ imply DM_RNG ++ imply DM_RTC ++ imply RTC_GOLDFISH ++ imply SCSI ++ imply SYS_NS16550 ++ imply SIFIVE_SERIAL ++ imply HTIF_CONSOLE if 64BIT ++ imply SYSRESET ++ imply SYSRESET_CMD_POWEROFF ++ imply SYSRESET_SYSCON ++ imply VIRTIO_MMIO ++ imply VIRTIO_PCI ++ imply VIRTIO_NET ++ imply VIRTIO_BLK ++ imply MTD_NOR_FLASH ++ imply CFI_FLASH ++ imply OF_HAS_PRIOR_STAGE ++ imply VIDEO ++ imply VIDEO_BOCHS ++ imply SYS_WHITE_ON_BLACK ++ imply PRE_CONSOLE_BUFFER ++ imply USB ++ imply USB_XHCI_HCD ++ imply USB_XHCI_PCI ++ imply USB_KEYBOARD ++ imply CMD_USB ++ imply UFS ++ imply UFS_PCI ++ ++endif diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_MAINTAINERS b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_MAINTAINERS new file mode 100644 index 000000000000..eb6ff84b2a3b --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_MAINTAINERS @@ -0,0 +1,9 @@ +--- board/emulation/bhyve-riscv/MAINTAINERS.orig ++++ board/emulation/bhyve-riscv/MAINTAINERS +@@ -0,0 +1,6 @@ ++RISCV 'BHYVE' BOARD ++M: Ruslan Bukin ++S: Maintained ++F: board/emulation/bhyve-riscv/ ++F: include/configs/bhyve-riscv.h ++F: configs/bhyve-riscv64_smode_defconfig diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Makefile b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Makefile new file mode 100644 index 000000000000..16e17e868885 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_Makefile @@ -0,0 +1,6 @@ +--- board/emulation/bhyve-riscv/Makefile.orig ++++ board/emulation/bhyve-riscv/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y += bhyve-riscv.o diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_bhyve-riscv.c b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_bhyve-riscv.c new file mode 100644 index 000000000000..22bb9648d717 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-board_emulation_bhyve-riscv_bhyve-riscv.c @@ -0,0 +1,75 @@ ++++ board/emulation/bhyve-riscv/bhyve-riscv.c.orig ++++ board/emulation/bhyve-riscv/bhyve-riscv.c +@@ -0,0 +1,72 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018, Bin Meng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if IS_ENABLED(CONFIG_MTD_NOR_FLASH) ++int is_flash_available(void) ++{ ++ if (!ofnode_equal(ofnode_by_compatible(ofnode_null(), "cfi-flash"), ++ ofnode_null())) ++ return 1; ++ ++ return 0; ++} ++#endif ++ ++int board_init(void) ++{ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ /* start usb so that usb keyboard can be used as input device */ ++ if (CONFIG_IS_ENABLED(USB_KEYBOARD)) ++ usb_init(); ++ ++ /* ++ * Make sure virtio bus is enumerated so that peripherals ++ * on the virtio bus can be discovered by their drivers ++ */ ++ virtio_init(); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_SPL ++u32 spl_boot_device(void) ++{ ++ /* RISC-V QEMU only supports RAM as SPL boot device */ ++ return BOOT_DEVICE_RAM; ++} ++#endif ++ ++#ifdef CONFIG_SPL_LOAD_FIT ++int board_fit_config_name_match(const char *name) ++{ ++ /* boot using first FIT config */ ++ return 0; ++} ++#endif ++ ++void *board_fdt_blob_setup(int *err) ++{ ++ *err = 0; ++ /* Stored the DTB address there during our init */ ++ return (void *)(ulong)gd->arch.firmware_fdt_addr; ++} diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-configs_bhyve-riscv64_smode_defconfig b/sysutils/u-boot-bhyve-riscv/files/patch-configs_bhyve-riscv64_smode_defconfig new file mode 100644 index 000000000000..f177586519b5 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-configs_bhyve-riscv64_smode_defconfig @@ -0,0 +1,44 @@ +--- configs/bhyve-riscv64_smode_defconfig.orig ++++ configs/bhyve-riscv64_smode_defconfig +@@ -0,0 +1,41 @@ ++CONFIG_RISCV=y ++CONFIG_SYS_MALLOC_LEN=0x800000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100200000 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_DEFAULT_DEVICE_TREE="bhyve-riscv" ++CONFIG_SYS_LOAD_ADDR=0x100000000 ++CONFIG_TARGET_BHYVE=y ++CONFIG_ARCH_RV64I=y ++CONFIG_RISCV_SMODE=y ++CONFIG_FIT=y ++CONFIG_SYS_BOOTM_LEN=0x4000000 ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DISPLAY_BOARDINFO=y ++CONFIG_CMD_BOOTEFI_SELFTEST=y ++CONFIG_CMD_NVEDIT_EFI=y ++# CONFIG_CMD_MII is not set ++# CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_DM_MTD=y ++CONFIG_FLASH_SHOW_PROGRESS=0 ++CONFIG_SYS_MAX_FLASH_BANKS=2 ++CONFIG_DEBUG_UART=y ++CONFIG_DEBUG_UART_BASE=0x10000 ++CONFIG_DEBUG_UART_NS16550=y ++CONFIG_DEBUG_UART_CLOCK=3686400 ++CONFIG_DEBUG_SBI_CONSOLE=n ++CONFIG_SERIAL=y ++CONFIG_BAUDRATE=115200 ++CONFIG_REQUIRE_SERIAL_CONSOLE=y ++CONFIG_SPECIFY_CONSOLE_INDEX=y ++CONFIG_SERIAL_PRESENT=y ++CONFIG_CONS_INDEX=1 ++CONFIG_DM=y ++CONFIG_DM_SERIAL=y ++CONFIG_SYS_NS16550_SERIAL=y ++CONFIG_SERIAL_SEARCH_ALL=y ++CONFIG_DM_DEBUG=n diff --git a/sysutils/u-boot-bhyve-riscv/files/patch-include_configs_bhyve-riscv.h b/sysutils/u-boot-bhyve-riscv/files/patch-include_configs_bhyve-riscv.h new file mode 100644 index 000000000000..4e352b4b6adc --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/files/patch-include_configs_bhyve-riscv.h @@ -0,0 +1,29 @@ +--- include/configs/bhyve-riscv.h.orig ++++ include/configs/bhyve-riscv.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2017 Tuomas Tynkkynen ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#include ++ ++#define CFG_SYS_SDRAM_BASE 0x100000000 ++#define CFG_SYS_SERIAL0 0x10000 ++#define CFG_SYS_NS16550_CLK 1000000 ++ ++#define BOOT_TARGET_DEVICES(func) \ ++ func(VIRTIO, virtio, 0) ++ ++#include ++ ++#define CFG_EXTRA_ENV_SETTINGS \ ++ "fdtfile=bhyve-riscv.dst\0" \ ++ "fdt_addr_r=0x100100000\0" \ ++ "kernel_addr_r=0x100200000\0" \ ++ BOOTENV ++ ++#endif /* __CONFIG_H */ diff --git a/sysutils/u-boot-bhyve-riscv/pkg-descr b/sysutils/u-boot-bhyve-riscv/pkg-descr new file mode 100644 index 000000000000..dc5832443a75 --- /dev/null +++ b/sysutils/u-boot-bhyve-riscv/pkg-descr @@ -0,0 +1,9 @@ +U-Boot loader for riscv bhyve + +The loader is configured to boot automatically from the first VirtIO block +device. Specify + + -o bootrom=$LOCALBASE/share/u-boot/u-boot-bhyve-riscv/u-boot.bin + +in bhyve(8) parameters. Note that this loader is experimental as the riscv +bhyve port is still under development.