From owner-freebsd-arch Wed Dec 26 8:16:33 2001 Delivered-To: freebsd-arch@freebsd.org Received: from prg.traveller.cz (prg.traveller.cz [193.85.2.77]) by hub.freebsd.org (Postfix) with ESMTP id 0CE1737B416 for ; Wed, 26 Dec 2001 08:16:30 -0800 (PST) Received: from prg.traveller.cz (localhost [127.0.0.1]) by prg.traveller.cz (8.12.1[KQ-CZ](1)/8.12.1/pukvis) with ESMTP id fBQGGTvT023792; Wed, 26 Dec 2001 17:16:29 +0100 (CET) Received: from localhost (mime@localhost) by prg.traveller.cz (8.12.1[KQ-CZ](1)/pukvis) with ESMTP id fBQGGSuG023789; Wed, 26 Dec 2001 17:16:28 +0100 (CET) Date: Wed, 26 Dec 2001 17:16:28 +0100 (CET) From: Michal Mertl To: John Hanley Cc: arch@freebsd.org Subject: Re: 64 bit counters In-Reply-To: <20011226005810.5475.qmail@web10102.mail.yahoo.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On Tue, 25 Dec 2001, John Hanley wrote: > My only caution is this: > > On some platforms, 64 bit ints are not atomically written. > First 32 bits is written, then the remaining 32. If, say, > only the bottom half of the kernel accesses the counter, What do you mean by "the bottom half of the kernel"? > then likely all is well. If an interrupt routine can read > or write in the middle of a non-atomic operation, then all > hell can break loose, in ways that are extremely difficult > to track down because they only happen rarely. > Well I didn't think of that but I believe it shouldn't be that much a problem. At most the counter could become wrong :-). -- Michal Mertl mime@traveller.cz To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message