From owner-svn-src-projects@freebsd.org Mon Jul 11 22:53:24 2016 Return-Path: Delivered-To: svn-src-projects@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1C20DB9235A for ; Mon, 11 Jul 2016 22:53:24 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E2A921C98; Mon, 11 Jul 2016 22:53:23 +0000 (UTC) (envelope-from nwhitehorn@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u6BMrNfj017463; Mon, 11 Jul 2016 22:53:23 GMT (envelope-from nwhitehorn@FreeBSD.org) Received: (from nwhitehorn@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u6BMrNvr017462; Mon, 11 Jul 2016 22:53:23 GMT (envelope-from nwhitehorn@FreeBSD.org) Message-Id: <201607112253.u6BMrNvr017462@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: nwhitehorn set sender to nwhitehorn@FreeBSD.org using -f From: Nathan Whitehorn Date: Mon, 11 Jul 2016 22:53:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r302597 - projects/powernv/powerpc/pseries X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jul 2016 22:53:24 -0000 Author: nwhitehorn Date: Mon Jul 11 22:53:22 2016 New Revision: 302597 URL: https://svnweb.freebsd.org/changeset/base/302597 Log: Fix OPAL XICS CPU assignment: CPU IDs need to be shifted left 2 bits. Modified: projects/powernv/powerpc/pseries/xics.c Modified: projects/powernv/powerpc/pseries/xics.c ============================================================================== --- projects/powernv/powerpc/pseries/xics.c Mon Jul 11 21:55:56 2016 (r302596) +++ projects/powernv/powerpc/pseries/xics.c Mon Jul 11 22:53:22 2016 (r302597) @@ -281,7 +281,7 @@ xicp_bind(device_t dev, u_int irq, cpuse error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu, XICP_PRIORITY, &status); else - error = opal_call(OPAL_SET_XIVE, irq, cpu, XICP_PRIORITY); + error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY); if (error < 0) panic("Cannot bind interrupt %d to CPU %d", irq, cpu); @@ -371,8 +371,12 @@ xicp_enable(device_t dev, u_int irq, u_i XICP_PRIORITY, &status); xicp_unmask(dev, irq); } else { - opal_call(OPAL_SET_XIVE, irq, cpu, XICP_PRIORITY); + status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY); /* Unmask implicit for OPAL */ + + if (status != 0) + panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq, + cpu, status); } } @@ -420,7 +424,7 @@ xicp_mask(device_t dev, u_int irq) } } KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt")); - opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu, 0xff); + opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff); } } @@ -443,7 +447,7 @@ xicp_unmask(device_t dev, u_int irq) } } KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt")); - opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu, + opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, XICP_PRIORITY); } }