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From: Juli Mallett <jmallett@FreeBSD.org>
To: Perforce Change Reviews <perforce@freebsd.org>
Subject: PERFORCE change 48810 for review
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http://perforce.freebsd.org/chv.cgi?CH=48810

Change 48810 by jmallett@jmallett_oingo on 2004/03/12 11:30:05

	Take out re-dirty WAR now that the TLB is kept coherent with
	half-valid entries.

Affected files ...

.. //depot/projects/mips/sys/mips/mips/tlb.c#24 edit

Differences ...

==== //depot/projects/mips/sys/mips/mips/tlb.c#24 (text+ko) ====

@@ -224,15 +224,6 @@
 
 /*
  * PTE was not dirty and is being written to.  XXX kernel only for now.
- *
- * XXX So it looks like something is broken above, because we end up
- * with duplicate EntryHi's in the TLB, and that's how we get here.
- * I think maybe the TLBL/TLBS routing is wrong, but I'm not prepared
- * to bet on that.  I will probably do a brief indirection though, and
- * check tlbp.  I guess ideally the TLBMiss handler would be called with
- * an Index, since we can obviously just choose a Random one, and so
- * forth, rather than using tlbwr, that'd make overloading said handler
- * a lot easier.  But I'm probably just a bad person.
  */
 void
 tlb_modified(void *badvaddr)
@@ -250,10 +241,8 @@
 		panic("write to invalid page");
 	if (pte_ro(pte))
 		panic("write to ro page");
-	if (pte_dirty(pte)) {
-		tlb_invalidate_all();
-		printf("dirty page caused a TLBMod\n");
-	}
+	if (pte_dirty(pte))
+		panic("dirty page caused a TLBMod");
 
 	/*
 	 * Mark the page dirty.