From owner-p4-projects@FreeBSD.ORG Tue Mar 4 15:06:07 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 524F91065673; Tue, 4 Mar 2008 15:06:07 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 109AB1065671 for ; Tue, 4 Mar 2008 15:06:07 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 003B58FC13 for ; Tue, 4 Mar 2008 15:06:06 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m24F66Fd010525 for ; Tue, 4 Mar 2008 15:06:06 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m24F66g6010523 for perforce@freebsd.org; Tue, 4 Mar 2008 15:06:06 GMT (envelope-from rrs@cisco.com) Date: Tue, 4 Mar 2008 15:06:06 GMT Message-Id: <200803041506.m24F66g6010523@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 136821 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Mar 2008 15:06:07 -0000 http://perforce.freebsd.org/chv.cgi?CH=136821 Change 136821 by rrs@rrs-mips2-jnpr on 2008/03/04 15:05:40 Ok, other weirdness of the oct16550 figured out. We will occasionaly, when getting a BREAK, get the proper indication from the IIR register, but the LSR tells us there is only a character. Which is the strange '0' character that accompanies each break. So transmute this to a break. We can always now get into the debugger with this fix :-) Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#17 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#17 (text+ko) ==== @@ -87,6 +87,9 @@ #define uart_getreg(bas, reg) \ bus_space_read_8((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) +int rrs_uart_debug=0; +int rrs_uart_show_tmit_too=0; + /* * Clear pending interrupts. THRE is cleared by reading IIR. Data * that may have been received gets lost here. @@ -632,6 +635,7 @@ iir = iir2 & IIR_IMASK; if (iir != IIR_NOPEND) { if (iir == IIR_RLS) { + unsigned int xc; lsr = uart_getreg(bas, OCT_REG_LSR); if (lsr & LSR_OE) ipend |= SER_INT_OVERRUN; @@ -647,7 +651,6 @@ * thats a bug). But regardless we don't * want to push in a subsequent 0. */ - unsigned int xc; xc = uart_getreg(bas, OCT_REG_RBR); if (xc != 0) { /* TSNH */ @@ -657,9 +660,25 @@ lsr = uart_getreg(bas, OCT_REG_LSR); } } - if (lsr & LSR_RXRDY) - ipend |= SER_INT_RXREADY; - + if (lsr & LSR_RXRDY) { + /* This is utterly wierd. If we get + * a IIR_RLS, we should ONT just + * read a LSR_RXRDY. So we will re-read the + * register and the character. If the + * char is 0, then its the 0 that accompanies + * the BREAK and the hardware just futzed. + * If its other than that, we loose and drop + * the character. + */ + xc = uart_getreg(bas, OCT_REG_RBR); + lsr = uart_getreg(bas, OCT_REG_LSR); + if (xc == 0) { + ipend |= SER_INT_BREAK; + } else { + /* TSNH, but neither should this whole block */ + printf("We loose a char %x\n", xc); + } + } } else if (iir == IIR_RXRDY) { ipend |= SER_INT_RXREADY; @@ -684,6 +703,8 @@ niir = uart_getreg(bas, OCT_REG_IIR); lsr = uart_getreg(bas, OCT_REG_LSR); usr = uart_getreg(bas, OCT_REG_USR); + printf("Got IIR_BUSY:%x niir:%x lsr:%x usr:%x\n", + iir2, niir, lsr, usr); } } uart_unlock(sc->sc_hwmtx);